Inventor · disambiguated record
Nigel Topham
Also filed as: TOPHAM NIGEL · TOPHAM NIGEL PETER
13 granted patents·2 pending applications·125 citations·filing 2001–2014
91Inventor score
Top patents by PatentIndex Score
15 records- 0188US7343471B2Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructionsPTS CORP·Filed 2005·Granted Mar 11, 2008·21 cites·28 claims
- 0281US7124279B2Processor and method for generating and storing compressed instructions in a program memory and decompressed instructions in an instruction cache wherein the decompressed instructions are assigned imaginary addresses derived from information stored in the program memory with the compressed instructionsPTS CORP·Filed 2001·Granted Oct 17, 2006·32 cites·24 claims
- 0377US8218635B2Systolic-array based systems and methods for performing block matching in motion compensationTOPHAM NIGEL·Filed 2006·Granted Jul 10, 2012·5 cites·15 claims
- 0475US6826677B2Renaming registers to values produced by instructions according to assigned produce sequence numberPTS CORP·Filed 2001·Granted Nov 30, 2004·23 cites·26 claims
- 0574US6944853B2Predicated execution of instructions in processorsPTS CORP·Filed 2001·Granted Sep 13, 2005·21 cites·23 claims
- 0669US7428630B2Processor adapted to receive different instruction setsALTERA CORP·Filed 2005·Granted Sep 23, 2008·4 cites·14 claims
- 0755US6993641B2Stall controlPTS CORP·Filed 2001·Granted Jan 31, 2006·5 cites·17 claims
- 0853US7805592B2Early resolving instructionsALTERA CORP·Filed 2002·Granted Sep 28, 2010·8 cites·18 claims
- 0949US9547493B2Self-timed user-extension instructions for a processing deviceSYNOPSYS INC·Filed 2014·Granted Jan 17, 2017·0 cites·21 claims
- 1049US7130989B2Processor adapted to receive different instruction setsPTS CORP·Filed 2001·Granted Oct 31, 2006·1 cites·15 claims
- 1149US6754806B2Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unitPTS CORP·Filed 2001·Granted Jun 22, 2004·1 cites·29 claims
- 1249US6732251B2Register file circuitryPTS CORP·Filed 2001·Granted May 4, 2004·4 cites·37 claims
- 1346US7512771B2Mapping circuitry and method comprising first and second candidate output value producing units, an in-range value determining unit, and an output value selection unitALTERA CORP·Filed 2004·Granted Mar 31, 2009·0 cites·24 claims
- 1440US2002144078A1Address translationSIROYAN LTD·Filed 2002·Application pending·0 cites
- 1537US2002144092A1Handling of loops in processorsSIROYAN LTD·Filed 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →