Inventor · disambiguated record
Mohamed Rabie
Also filed as: RABIE MOHAMED · RABIE MOHAMED A · RABIE MOHAMED ABDELMAKSOUD MOHAMED
6 granted patents·5 pending applications·11 citations·filing 2014–2024
73Inventor score
Top patents by PatentIndex Score
11 records- 0193US11804452B2Pic structure having barrier surrounding opening for optical element to prevent stress damageGLOBALFOUNDRIES US INC·Filed 2021·Granted Oct 31, 2023·8 cites·20 claims
- 0276US11276651B2IC product comprising a single active fin FinFET device and an electrically inactive fin stress reduction structureGLOBALFOUNDRIES US INC·Filed 2020·Granted Mar 15, 2022·1 cites·17 claims
- 0370US10068859B1Crack trapping in semiconductor device structuresGLOBALFOUNDRIES INC·Filed 2017·Granted Sep 4, 2018·2 cites·16 claims
- 0469US11569180B2Corner structures for an optical fiber groove and manufacturing methods thereofGLOBALFOUNDRIES US INC·Filed 2021·Granted Jan 31, 2023·0 cites·20 claims
- 0561US11145606B1Corner structures for an optical fiber grooveGLOBALFOUNDRIES US INC·Filed 2020·Granted Oct 12, 2021·0 cites·16 claims
- 0661US2025393231A1Semiconductor device gate skirt modificationIBM·Filed 2024·Application pending·0 cites
- 0759US2025393265A1Stressed nanosheet channelsIBM·Filed 2024·Application pending·0 cites
- 0840US10923397B2Through-substrate via structures in semiconductor devicesGLOBALFOUNDRIES INC·Filed 2018·Granted Feb 16, 2021·0 cites·20 claims
- 0937US2015228555A1Structure and method of cancelling tsv-induced substrate stressGLOBALFOUNDRIES INC·Filed 2014·Application pending·0 cites
- 1031US2017373019A1Method to mitigate chip package interaction risk on die corner using reinforcing tilesGLOBALFOUNDRIES INC·Filed 2016·Application pending·0 cites
- 1125US2017033061A1Mitigating transient tsv-induced ic substrate noise and resulting devicesGLOBALFOUNDRIES INC·Filed 2015·Application pending·0 cites
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