Inventor · disambiguated record
Robert Douglas Clancy
Also filed as: CLANCY ROBERT D · CLANCY ROBERT DOUGLAS
10 granted patents·10 pending applications·9 citations·filing 2005–2021
80Inventor score
Technology areasG06F
Files withQUALCOMM INC13MICROSOFT TECHNOLOGY LICENSING LLC4CLANCY ROBERT D2DIEFFENDERFER JAMES NORRIS1
Top patents by PatentIndex Score
20 records- 0170US10956162B2Operand-based reach explicit dataflow processors, and related methods and computer-readable mediaMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Mar 23, 2021·1 cites·30 claims
- 0270US9110830B2Determining cache hit/miss of aliased addresses in virtually-tagged cache(s), and related systems and methodsDIEFFENDERFER JAMES NORRIS·Filed 2012·Granted Aug 18, 2015·3 cites·29 claims
- 0366US7650466B2Method and apparatus for managing cache partitioning using a dynamic boundaryQUALCOMM INC·Filed 2005·Granted Jan 19, 2010·3 cites·24 claims
- 0464US7725625B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2008·Granted May 25, 2010·2 cites·20 claims
- 0555US11487545B2Processor branch prediction circuit employing back-invalidation of prediction cache entries based on decoded branch instructions and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Granted Nov 1, 2022·0 cites·20 claims
- 0649US10838731B2Branch prediction based on load-path historyQUALCOMM INC·Filed 2018·Granted Nov 17, 2020·0 cites·33 claims
- 0748US10318436B2Precise invalidation of virtually tagged cachesQUALCOMM INC·Filed 2017·Granted Jun 11, 2019·0 cites·30 claims
- 0848US7454538B2Latency insensitive FIFO signaling protocolQUALCOMM INC·Filed 2005·Granted Nov 18, 2008·0 cites·14 claims
- 0945US2016055003A1Branch prediction using least-recently-used (lru)-class linked list branch predictors, and related circuits, methods, and computer-readable mediaQUALCOMM INC·Filed 2014·Application pending·0 cites
- 1043US2022283811A1Loop buffering employing loop characteristic prediction in a processor for optimizing loop buffer performanceMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 1143US2019155608A1Fast pipeline restart in processor with decoupled fetcherQUALCOMM INC·Filed 2018·Application pending·0 cites
- 1242US2022318139A1Processor supporting translation lookaside buffer (tlb) modification instruction for updating hardware-managed tlb and related methodsMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2021·Application pending·0 cites
- 1341US8612690B2Method for filtering traffic to a physically-tagged data cacheCLANCY ROBERT D·Filed 2012·Granted Dec 17, 2013·0 cites·24 claims
- 1440US10114750B2Preventing the displacement of high temporal locality of reference data fill buffersCLANCY ROBERT D·Filed 2012·Granted Oct 30, 2018·0 cites·25 claims
- 1539US2019294443A1Providing early pipeline optimization of conditional instructions in processor-based systemsQUALCOMM INC·Filed 2018·Application pending·0 cites
- 1637US2018089094A1Precise invalidation of virtually tagged cachesQUALCOMM INC·Filed 2016·Application pending·0 cites
- 1737US2017046266A1Way Mispredict Mitigation on a Way Predicted CacheQUALCOMM INC·Filed 2016·Application pending·0 cites
- 1836US2016350116A1Mitigating wrong-path effects in branch predictionQUALCOMM INC·Filed 2015·Application pending·0 cites
- 1936US2017046278A1Method and apparatus for updating replacement policy information for a fully associative buffer cacheQUALCOMM INC·Filed 2016·Application pending·0 cites
- 2035US2017083333A1Branch target instruction cache (btic) to store a conditional branch instructionQUALCOMM INC·Filed 2015·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →