Inventor · disambiguated record
Gary K. Yeap
Also filed as: YEAP GARY · YEAP GARY K
16 granted patents·481 citations·filing 1995–2023
93Inventor score
Files withSYNOPSYS INC7MOTOROLA INC3MONTEREY DESIGN SYSTEMS2MONTEREY DESIGN SYSTEMS INC2LEE JOHN JUNG1
Top patents by PatentIndex Score
16 records- 0191US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 0288US6961916B2Placement method for integrated circuit design using topo-clusteringSYNOPSYS INC·Filed 2002·Granted Nov 1, 2005·45 cites·7 claims
- 0387US6442743B1Placement method for integrated circuit design using topo-clusteringMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Aug 27, 2002·126 cites·13 claims
- 0477US12118283B1Automatic channel identification of high-bandwidth memory channels for auto-routingSYNOPSYS INC·Filed 2023·Granted Oct 15, 2024·0 cites·20 claims
- 0577US8726215B2Standard cell placement technique for double patterning technologyLEE JOHN JUNG·Filed 2011·Granted May 13, 2014·15 cites·24 claims
- 0672US7937677B2Design-for-test-aware hierarchical design planningSYNOPSYS INC·Filed 2008·Granted May 3, 2011·9 cites·24 claims
- 0771US8392870B2Two-chip co-design and co-optimization in three-dimensional integrated circuit net assignmentZHANG YIFAN·Filed 2011·Granted Mar 5, 2013·5 cites·18 claims
- 0868US11816407B1Automatic channel identification of high-bandwidth memory channels for auto-routingSYNOPSYS INC·Filed 2021·Granted Nov 14, 2023·0 cites·11 claims
- 0958US12489021B1Determining a density of through-silicon vias in integrated circuitsSYNOPSYS INC·Filed 2022·Granted Dec 2, 2025·0 cites·14 claims
- 1056US10922467B2Methodology using Fin-FET transistorsSYNOPSYS INC·Filed 2019·Granted Feb 16, 2021·0 cites·27 claims
- 1155US5673420AMethod of generating power vectors for cell power dissipation simulationMOTOROLA INC·Filed 1996·Granted Sep 30, 1997·34 cites·14 claims
- 1249US6192508B1Method for logic optimization for improving timing and congestion during placement in integrated circuit designMONTEREY DESIGN SYSTEMS·Filed 1998·Granted Feb 20, 2001·23 cites·18 claims
- 1347US10817636B2Methodology using Fin-FET transistorsSYNOPSYS INC·Filed 2015·Granted Oct 27, 2020·0 cites·45 claims
- 1437US6385760B2System and method for concurrent placement of gates and associated wiringMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted May 7, 2002·9 cites·8 claims
- 1535US5825644AMethod for encoding a state machineMOTOROLA INC·Filed 1996·Granted Oct 20, 1998·7 cites·17 claims
- 1629US5740407AMethod of generating power vectors for circuit power dissipation simulation having both combinational and sequential logic circuitsMOTOROLA INC·Filed 1995·Granted Apr 14, 1998·6 cites·13 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →