Inventor · disambiguated record
Gururaj K. Shamanna
Also filed as: SHAMANNA GURURAJ · SHAMANNA GURURAJ K
9 granted patents·3 pending applications·88 citations·filing 1998–2022
81Inventor score
Top patents by PatentIndex Score
12 records- 0177US9570158B1Output latch for accelerated memory accessQUALCOMM INC·Filed 2016·Granted Feb 14, 2017·7 cites·30 claims
- 0275US6321297B1Avoiding tag compares during writes in multi-level cache hierarchyINTEL CORP·Filed 1998·Granted Nov 20, 2001·80 cites·17 claims
- 0368US11927982B2Keeper-free integrated clock gate circuitINTEL CORP·Filed 2020·Granted Mar 12, 2024·1 cites·22 claims
- 0453US12367926B2Apparatus and method to optimize sense-amp enable pulse-width in SRAM arraysINTEL CORP·Filed 2021·Granted Jul 22, 2025·0 cites·21 claims
- 0551US9921630B2Apparatus and method for reducing leakage power of a circuitINTEL CORP·Filed 2015·Granted Mar 20, 2018·0 cites·21 claims
- 0648US9207750B2Apparatus and method for reducing leakage power of a circuitINTEL CORP·Filed 2012·Granted Dec 8, 2015·0 cites·20 claims
- 0746US2022375898A1Programmable capacitance in three-dimensional stacked die architectureINTEL CORP·Filed 2021·Application pending·0 cites
- 0841US10996709B2Low power clock gate circuitINTEL CORP·Filed 2019·Granted May 4, 2021·0 cites·20 claims
- 0941US10269417B2Apparatus for adaptive write assist for memoryINTEL CORP·Filed 2014·Granted Apr 23, 2019·0 cites·20 claims
- 1039US2023343389A1Self-resetting clock generatorINTEL CORP·Filed 2022·Application pending·0 cites
- 1136US10140044B2Efficient memory bank designQUALCOMM INC·Filed 2016·Granted Nov 27, 2018·0 cites·21 claims
- 1234US2023395140A1Variation tolerant reconfigurable replica bitline circuitsINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →