Inventor · disambiguated record
Ting-Pwu Yen
Also filed as: YEN TING · YEN TING P · YEN TING-PWU
20 granted patents·602 citations·filing 1989–2006
96Inventor score
Files withPARADIGM TECHNOLOGY INC10CYPRESS SEMICONDUCTOR CORP4INTEGRATED MEMORY TECH INC3INTEGRATED DEVICE TECH1NORTH AMERICAN PHILIPS CORP SI1
Top patents by PatentIndex Score
20 records- 0191US5656861ASelf-aligning contact and interconnect structurePARADIGM TECHNOLOGY INC·Filed 1995·Granted Aug 12, 1997·134 cites·13 claims
- 0285US7407857B2Method of making a scalable flash EEPROM memory cell with notched floating gate and graded source regionINTEGRATED MEMORY TECH INC·Filed 2006·Granted Aug 5, 2008·10 cites·16 claims
- 0380US6900999B1Ternary content addressable memory (TCAM) cells with small footprint size and efficient layout aspect ratioINTEGRATED DEVICE TECH·Filed 2003·Granted May 31, 2005·24 cites·56 claims
- 0479US5348897ATransistor fabrication methods using overlapping masksPARADIGM TECHNOLOGY INC·Filed 1992·Granted Sep 20, 1994·44 cites·29 claims
- 0574US5977638AEdge metal for interconnect layersCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Nov 2, 1999·49 cites·44 claims
- 0674US5172211AHigh resistance polysilicon load resistorPARADIGM TECHNOLOGY INC·Filed 1990·Granted Dec 15, 1992·41 cites·21 claims
- 0772US5168076AMethod of fabricating a high resistance polysilicon load resistorPARADIGM TECHNOLOGY INC·Filed 1991·Granted Dec 1, 1992·36 cites·7 claims
- 0870US7009244B2Scalable flash EEPROM memory cell with notched floating gate and graded source regionINTEGRATED MEMORY TECH INC·Filed 2004·Granted Mar 7, 2006·12 cites·8 claims
- 0970US5483104ASelf-aligning contact and interconnect structurePARADIGM TECHNOLOGY INC·Filed 1992·Granted Jan 9, 1996·38 cites·10 claims
- 1066US5166771ASelf-aligning contact and interconnect structurePARADIGM TECHNOLOGY INC·Filed 1990·Granted Nov 24, 1992·35 cites·25 claims
- 1163US5620919AMethods for fabricating integrated circuits including openings to transistor regionsPARADIGM TECHNOLOGY INC·Filed 1995·Granted Apr 15, 1997·28 cites·1 claims
- 1262US5340774ASemiconductor fabrication technique using local planarization with self-aligned transistorsPARADIGM TECHNOLOGY INC·Filed 1993·Granted Aug 23, 1994·27 cites·22 claims
- 1361US5015604AFabrication method using oxidation to control size of fusible linkNORTH AMERICAN PHILIPS CORP SI·Filed 1989·Granted May 14, 1991·25 cites·12 claims
- 1456US5465004AProgrammable semiconductor integrated circuits having fusible linksPHILIPS CORP·Filed 1995·Granted Nov 7, 1995·22 cites·8 claims
- 1555US5124774ACompact SRAM cell layoutPARADIGM TECHNOLOGY INC·Filed 1990·Granted Jun 23, 1992·25 cites·16 claims
- 1654US5861676AMethod of forming robust interconnect and contact structures in a semiconductor and/or integrated circuitCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jan 19, 1999·19 cites·20 claims
- 1748US7199424B2Scalable flash EEPROM memory cell with notched floating gate and graded source regionINTEGRATED MEMORY TECH INC·Filed 2006·Granted Apr 3, 2007·0 cites·14 claims
- 1847US5477074ASemiconductor structure using local planarization with self-aligned transistorsPARADIGM TECHNOLOGY INC·Filed 1994·Granted Dec 19, 1995·13 cites·8 claims
- 1944US6579777B1Method of forming local oxidation with sloped silicon recessCYPRESS SEMICONDUCTOR CORP·Filed 1996·Granted Jun 17, 2003·12 cites·20 claims
- 2039US5965924AMetal plug local interconnectCYPRESS SEMICONDUCTOR CORP·Filed 1997·Granted Oct 12, 1999·8 cites·17 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →