Inventor · disambiguated record
Paul Breuder
Also filed as: BREUDER PAUL · BREUDER PAUL D
11 granted patents·241 citations·filing 1997–2003
92Inventor score
Files withINTEL CORP11
Top patents by PatentIndex Score
11 records- 0190US6732242B2External bus transaction scheduling systemINTEL CORP·Filed 2002·Granted May 4, 2004·63 cites·26 claims
- 0289US6668309B2Snoop blocking for cache coherencyINTEL CORP·Filed 2003·Granted Dec 23, 2003·48 cites·11 claims
- 0376US6578116B2Snoop blocking for cache coherencyINTEL CORP·Filed 2002·Granted Jun 10, 2003·18 cites·10 claims
- 0468US6735675B2Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 2003·Granted May 11, 2004·10 cites·18 claims
- 0566US6578114B2Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 2002·Granted Jun 10, 2003·9 cites·36 claims
- 0659US6078981ATransaction stall technique to prevent livelock in multiple-processor systemsINTEL CORP·Filed 1997·Granted Jun 20, 2000·33 cites·15 claims
- 0754US6378048B1“SLIME” cache coherency system for agents with multi-layer cachesINTEL CORP·Filed 1998·Granted Apr 23, 2002·29 cites·23 claims
- 0848US6434677B1Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 1999·Granted Aug 13, 2002·15 cites·15 claims
- 0946US6412091B2Error correction system in a processing agent having minimal delayINTEL CORP·Filed 2001·Granted Jun 25, 2002·3 cites·19 claims
- 1043US6460119B1Snoop blocking for cache coherencyINTEL CORP·Filed 1998·Granted Oct 1, 2002·11 cites·14 claims
- 1132US6269465B1Error correction system in a processing agent having minimal delayINTEL CORP·Filed 1998·Granted Jul 31, 2001·2 cites·23 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →