Inventor · disambiguated record
Yim Pun
Also filed as: PUN YIM
7 granted patents·5 pending applications·88 citations·filing 1992–2008
85Inventor score
Top patents by PatentIndex Score
12 records- 0177US8087024B2Multiple multi-threaded processors having an L1 instruction cache and a shared L2 instruction cacheLAKSHMANAMURTHY SRIDHAR·Filed 2008·Granted Dec 27, 2011·7 cites·5 claims
- 0277US5343086AAutomatic voltage detector control circuitryINTEL CORP·Filed 1992·Granted Aug 30, 1994·45 cites·16 claims
- 0365US7251219B2Method and apparatus to communicate flow control information in a duplex network processor systemINTEL CORP·Filed 2002·Granted Jul 31, 2007·10 cites·8 claims
- 0464US7039054B2Method and apparatus for header splitting/splicing and automating recovery of transmit resources on a per-transmit granularityINTEL CORP·Filed 2002·Granted May 2, 2006·10 cites·22 claims
- 0562US7313140B2Method and apparatus to assemble data segments into full packets for efficient packet-based classificationINTEL CORP·Filed 2002·Granted Dec 25, 2007·8 cites·20 claims
- 0659US7103821B2Method and apparatus for improving network router line rate performance by an improved system for error checkingINTEL CORP·Filed 2002·Granted Sep 5, 2006·7 cites·28 claims
- 0748US7536692B2Thread-based engine cache partitioningINTEL CORP·Filed 2003·Granted May 19, 2009·1 cites·14 claims
- 0843US2005050306A1Executing instructions on a processorFiled 2003·Application pending·0 cites
- 0943US2004252687A1Method and process for scheduling data packet collectionFiled 2003·Application pending·0 cites
- 1042US2005108479A1Servicing engine cache requestsFiled 2003·Application pending·0 cites
- 1142US2005102474A1Dynamically caching engine instructionsFiled 2003·Application pending·0 cites
- 1241US2004213219A1Method and apparatus to handle the flow control in a cascaded configurationFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →