Inventor · disambiguated record
Michael W. Rhodehamel
Also filed as: RHODEHAMEL MICHAEL · RHODEHAMEL MICHAEL W
31 granted patents·1,463 citations·filing 1994–2006
98Inventor score
Files withINTEL CORP31
Top patents by PatentIndex Score
31 records- 0196US5623628AComputer system and method for maintaining memory consistency in a pipelined, non-blocking caching bus request queueINTEL CORP·Filed 1994·Granted Apr 22, 1997·296 cites·13 claims
- 0291USRE38388EMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 2001·Granted Jan 13, 2004·50 cites·73 claims
- 0391US5754833AMethod and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratioINTEL CORP·Filed 1997·Granted May 19, 1998·77 cites·22 claims
- 0484US5581782AComputer system with distributed bus arbitration scheme for symmetric and priority agentsINTEL CORP·Filed 1995·Granted Dec 3, 1996·117 cites·48 claims
- 0583US5615343AMethod and apparatus for performing deferred transactionsINTEL CORP·Filed 1994·Granted Mar 25, 1997·69 cites·31 claims
- 0680US5796977AHighly pipelined bus architectureINTEL CORP·Filed 1996·Granted Aug 18, 1998·89 cites·16 claims
- 0779US7802083B2Utilization based installation on a computing systemINTEL CORP·Filed 2006·Granted Sep 21, 2010·10 cites·24 claims
- 0877US5715428AApparatus for maintaining multilevel cache hierarchy coherency in a multiprocessor computer systemINTEL CORP·Filed 1996·Granted Feb 3, 1998·82 cites·35 claims
- 0971US5832534AMethod and apparatus for maintaining cache coherency using a single controller for multiple cache memoriesINTEL CORP·Filed 1995·Granted Nov 3, 1998·43 cites·6 claims
- 1071US5636374AMethod and apparatus for performing operations based upon the addresses of microinstructionsINTEL CORP·Filed 1995·Granted Jun 3, 1997·68 cites·48 claims
- 1170US5809524AMethod and apparatus for cache memory replacement line identificationINTEL CORP·Filed 1997·Granted Sep 15, 1998·57 cites·16 claims
- 1270US5682516AComputer system that maintains system wide cache coherency during deferred communication transactionsINTEL CORP·Filed 1994·Granted Oct 28, 1997·58 cites·38 claims
- 1367US5572702AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1994·Granted Nov 5, 1996·40 cites·30 claims
- 1466US5548733AMethod and apparatus for dynamically controlling the current maximum depth of a pipe lined computer bus systemINTEL CORP·Filed 1994·Granted Aug 20, 1996·34 cites·31 claims
- 1563US6061599AAuto-configuration support for multiple processor-ready pair or FRC-master/checker pairINTEL CORP·Filed 1996·Granted May 9, 2000·31 cites·36 claims
- 1663US5764934AProcessor subsystem for use with a universal computer architectureINTEL CORP·Filed 1996·Granted Jun 9, 1998·41 cites·18 claims
- 1762US5797026AMethod and apparatus for self-snooping a bus during a boundary transactionINTEL CORP·Filed 1997·Granted Aug 18, 1998·41 cites·30 claims
- 1861US5802132AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1996·Granted Sep 1, 1998·33 cites·22 claims
- 1959US5845107ASignaling protocol conversion between a processor and a high-performance system busINTEL CORP·Filed 1996·Granted Dec 1, 1998·36 cites·16 claims
- 2056US5701503AMethod and apparatus for transferring information between a processor and a memory systemINTEL CORP·Filed 1994·Granted Dec 23, 1997·27 cites·22 claims
- 2154US5515516AInitialization mechanism for symmetric arbitration agentsINTEL CORP·Filed 1994·Granted May 7, 1996·22 cites·41 claims
- 2250US6055656AControl register bus access through a standardized test access portINTEL CORP·Filed 1995·Granted Apr 25, 2000·27 cites·10 claims
- 2349US5909699AMethod and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistencyINTEL CORP·Filed 1996·Granted Jun 1, 1999·19 cites·24 claims
- 2446US6009477ABus agent providing dynamic pipeline depth controlINTEL CORP·Filed 1998·Granted Dec 28, 1999·17 cites·3 claims
- 2546US5784579AMethod and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depthINTEL CORP·Filed 1996·Granted Jul 21, 1998·18 cites·11 claims
- 2646US5778441AMethod and apparatus for accessing split lock variables in a computer systemINTEL CORP·Filed 1996·Granted Jul 7, 1998·18 cites·11 claims
- 2742US5896513AComputer system providing a universal architecture adaptive to a variety of processor types and bus protocolsINTEL CORP·Filed 1996·Granted Apr 20, 1999·14 cites·20 claims
- 2840US6114887AApparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking schemeINTEL CORP·Filed 1997·Granted Sep 5, 2000·10 cites·24 claims
- 2940US5901297AInitialization mechanism for symmetric arbitration agentsINTEL CORP·Filed 1997·Granted May 4, 1999·9 cites·6 claims
- 3036US5948088ABus system providing dynamic control of pipeline depth for a multi-agent computerINTEL CORP·Filed 1997·Granted Sep 7, 1999·5 cites·14 claims
- 3135US5761449ABus system providing dynamic control of pipeline depth for a multi-agent computerINTEL CORP·Filed 1997·Granted Jun 2, 1998·5 cites·3 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →