Inventor · disambiguated record
Douglas Brisbin
Also filed as: BRISBIN DOUGLAS · BRISBIN DOUGLAS J
12 granted patents·197 citations·filing 2001–2009
91Inventor score
Top patents by PatentIndex Score
12 records- 0191US6566710B1Power MOSFET cell with a crossed bar shaped body contact areaNAT SEMICONDUCTOR CORP·Filed 2001·Granted May 20, 2003·68 cites·6 claims
- 0290US7180140B1PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in and method for designing and manufacturing such deviceNAT SEMICONDUCTOR CORP·Filed 2004·Granted Feb 20, 2007·44 cites·15 claims
- 0385US7718448B1Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arraysNAT SEMICONDUCTOR CORP·Filed 2005·Granted May 18, 2010·11 cites·20 claims
- 0472US6946706B1LDMOS transistor structure for improving hot carrier reliabilityNAT SEMICONDUCTOR CORP·Filed 2003·Granted Sep 20, 2005·19 cites·16 claims
- 0572US6548839B1LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliabilityNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 15, 2003·18 cites·9 claims
- 0670US6727547B1Method and device for improving hot carrier reliability of an LDMOS transistor using drain ring over-drive biasNAT SEMICONDUCTOR CORP·Filed 2002·Granted Apr 27, 2004·15 cites·8 claims
- 0760US7645657B2MOS transistor and method of forming the MOS transistor with a SiON etch stop layer that protects the transistor from PID and hot carrier degradationNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jan 12, 2010·1 cites·20 claims
- 0860US7214992B1Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regionsNAT SEMICONDUCTOR CORP·Filed 2004·Granted May 8, 2007·9 cites·10 claims
- 0956US6903979B1Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate currentNAT SEMICONDUCTOR CORP·Filed 2003·Granted Jun 7, 2005·9 cites·7 claims
- 1050US7560348B2Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-inNAT SEMICONDUCTOR CORP·Filed 2007·Granted Jul 14, 2009·0 cites·7 claims
- 1147US8086979B2Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-inBRISBIN DOUGLAS·Filed 2009·Granted Dec 27, 2011·0 cites·11 claims
- 1240US8471369B1Method and apparatus for reducing plasma process induced damage in integrated circuitsMCCULLOH HEATHER·Filed 2004·Granted Jun 25, 2013·3 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →