Inventor · disambiguated record
John D. Walker
Also filed as: WALKER JOHN D · WALKER JOHN DE Q · WALKER JOHN DE QUINCEY
10 granted patents·1 pending application·361 citations·filing 1993–2004
92Inventor score
Top patents by PatentIndex Score
11 records- 0191US5966599AMethod for fabricating a low trigger voltage silicon controlled rectifier and thick field deviceLSI LOGIC CORP·Filed 1996·Granted Oct 12, 1999·115 cites·28 claims
- 0286US5821572ASimple BICMOS process for creation of low trigger voltage SCR and zener diode pad protectionSYMBIOS INC·Filed 1996·Granted Oct 13, 1998·60 cites·17 claims
- 0384US6130117ASimple bicmos process for creation of low trigger voltage SCR and zener diode pad protectionLSI LOGIC CORP·Filed 1998·Granted Oct 10, 2000·53 cites·6 claims
- 0483US5498892ALightly doped drain ballast resistorNCR CORP·Filed 1993·Granted Mar 12, 1996·59 cites·20 claims
- 0577US6822282B2Analog capacitor in dual damascene processLSI LOGIC CORP·Filed 2003·Granted Nov 23, 2004·22 cites·2 claims
- 0674US6855586B2Low voltage breakdown element for ESD trigger deviceLSI LOGIC CORP·Filed 2003·Granted Feb 15, 2005·16 cites·11 claims
- 0771US6710990B2Low voltage breakdown element for ESD trigger deviceLSI LOGIC CORP·Filed 2002·Granted Mar 23, 2004·14 cites·19 claims
- 0863US6596579B1Method of forming analog capacitor dual damascene processLSI LOGIC CORP·Filed 2001·Granted Jul 22, 2003·10 cites·16 claims
- 0960US7183791B2Reliability circuit for applying an AC stress signal or DC measurement to a transistor deviceLSI LOGIC CORP·Filed 2004·Granted Feb 27, 2007·8 cites·19 claims
- 1050US7176082B2Analog capacitor in dual damascene processLSI LOGIC CORP·Filed 2004·Granted Feb 13, 2007·4 cites·4 claims
- 1134US2004073412A1Negative bias temperature instability effect modelingFiled 2002·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →