Inventor · disambiguated record
Matthew M. Ziegler
Also filed as: ZIEGLER MATTHEW M · ZIEGLER MATTHEW MANTELL
22 granted patents·2 pending applications·150 citations·filing 2010–2022
94Inventor score
Top patents by PatentIndex Score
24 records- 0194US8839162B2Specifying circuit level connectivity during circuit design synthesisAMUNDSON MICHAEL D·Filed 2010·Granted Sep 16, 2014·59 cites·25 claims
- 0293US8271920B2Converged large block and structured synthesis for high performance microprocessor designsCHO MINSIK·Filed 2010·Granted Sep 18, 2012·34 cites·22 claims
- 0389US10083268B2Scheduling simultaneous optimization of multiple very-large-scale-integration designsIBM·Filed 2016·Granted Sep 25, 2018·6 cites·20 claims
- 0489US8495552B1Structured latch and local-clock-buffer planningCHO MINSIK·Filed 2012·Granted Jul 23, 2013·13 cites·15 claims
- 0586US9600623B1Scheduling simultaneous optimization of multiple very-large-scale-integration designsIBM·Filed 2015·Granted Mar 21, 2017·5 cites·20 claims
- 0684US9934344B2Enhanced parameter tuning for very-large-scale integration synthesisIBM·Filed 2016·Granted Apr 3, 2018·3 cites·14 claims
- 0784US9529951B2Synthesis tuning system for VLSI design optimizationIBM·Filed 2014·Granted Dec 27, 2016·7 cites·16 claims
- 0882US9703920B2Intra-run design decision process for circuit synthesisIBM·Filed 2015·Granted Jul 11, 2017·3 cites·12 claims
- 0982US8516412B2Soft hierarchy-based physical synthesis for large-scale, high-performance circuitsCHO MINSIK·Filed 2011·Granted Aug 20, 2013·8 cites·23 claims
- 1080US10002221B2Enhanced parameter tuning for very-large-scale integration synthesisIBM·Filed 2017·Granted Jun 19, 2018·2 cites·20 claims
- 1177US9910949B2Synthesis tuning system for VLSI design optimizationIBM·Filed 2016·Granted Mar 6, 2018·2 cites·16 claims
- 1274US10296691B2Optimizing the layout of circuits based on multiple design constraintsIBM·Filed 2016·Granted May 21, 2019·2 cites·18 claims
- 1370US9619602B2Enhanced parameter tuning for very-large-scale integration synthesisIBM·Filed 2015·Granted Apr 11, 2017·1 cites·12 claims
- 1470US8566761B2Network flow based datapath bit slicingXIANG HUA·Filed 2011·Granted Oct 22, 2013·3 cites·18 claims
- 1561US8756541B2Relative ordering circuit synthesisCHO MINSIK·Filed 2012·Granted Jun 17, 2014·1 cites·23 claims
- 1659US10789400B2Scheduling simultaneous optimization of multiple very-large-scale-integration designsIBM·Filed 2018·Granted Sep 29, 2020·0 cites·20 claims
- 1759US8954914B2Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip designIBM·Filed 2013·Granted Feb 10, 2015·1 cites·23 claims
- 1858US11636245B2Methods and systems for leveraging computer-aided design variability in synthesis tuningIBM·Filed 2021·Granted Apr 25, 2023·0 cites·21 claims
- 1958US9582627B2Enhanced parameter tuning for very-large-scale integration synthesisIBM·Filed 2014·Granted Feb 28, 2017·0 cites·8 claims
- 2053US9690900B2Intra-run design decision process for circuit synthesisIBM·Filed 2015·Granted Jun 27, 2017·0 cites·8 claims
- 2150US10263519B2Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate timeIBM·Filed 2015·Granted Apr 16, 2019·0 cites·16 claims
- 2249US9660530B2Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate timeIBM·Filed 2015·Granted May 23, 2017·0 cites·6 claims
- 2349US2013326451A1Structured Latch and Local-Clock-Buffer PlanningCHO MINSIK·Filed 2012·Application pending·0 cites
- 2448US2023315529A1Ticket queue for controlling compute process access to shared data and compute resourcesIBM·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →