Inventor · disambiguated record
Michael A. Fetterman
Also filed as: FETTERMAN MICHAEL · FETTERMAN MICHAEL A · FETTERMAN MICHAEL ALAN
76 granted patents·5 pending applications·3,213 citations·filing 1993–2024
99Inventor score
Top patents by PatentIndex Score
81 records- 0196US5721855AMethod for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder bufferINTEL CORP·Filed 1996·Granted Feb 24, 1998·335 cites·23 claims
- 0295US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 0392US10699427B2Method and apparatus for obtaining sampled positions of texturing operationsNVIDIA CORP·Filed 2019·Granted Jun 30, 2020·9 cites·20 claims
- 0491US10424074B1Method and apparatus for obtaining sampled positions of texturing operationsNVIDIA CORP·Filed 2018·Granted Sep 24, 2019·7 cites·20 claims
- 0591US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 0689US5555432ACircuit and method for scheduling instructions by predicting future availability of resources required for executionINTEL CORP·Filed 1994·Granted Sep 10, 1996·108 cites·7 claims
- 0788US5778245AMethod and apparatus for dynamic allocation of multiple buffers in a processorINTEL CORP·Filed 1994·Granted Jul 7, 1998·131 cites·22 claims
- 0887US9471307B2System and processor that include an implementation of decoupled pipelinesNVIDIA CORP·Filed 2014·Granted Oct 18, 2016·10 cites·16 claims
- 0986US9600235B2Technique for performing arbitrary width integer arithmetic operations using fixed width elementsNVIDIA CORP·Filed 2013·Granted Mar 21, 2017·9 cites·21 claims
- 1086US6047369AFlag renaming and flag masks within register alias tableINTEL CORP·Filed 1994·Granted Apr 4, 2000·122 cites·48 claims
- 1185US5889982AMethod and apparatus for generating event handler vectors based on both operating mode and event typeINTEL CORP·Filed 1995·Granted Mar 30, 1999·129 cites·67 claims
- 1285US5627985ASpeculative and committed resource files in an out-of-order processorINTEL CORP·Filed 1994·Granted May 6, 1997·112 cites·33 claims
- 1384US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 1483US9262174B2Dynamic bank mode addressing for memory accessFETTERMAN MICHAEL·Filed 2012·Granted Feb 16, 2016·8 cites·24 claims
- 1583US5404473AApparatus and method for handling string operations in a pipelined processorINTEL CORP·Filed 1994·Granted Apr 4, 1995·109 cites·37 claims
- 1681US6079014AProcessor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural stateINTEL CORP·Filed 1997·Granted Jun 20, 2000·101 cites·23 claims
- 1781US5584038AEntry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversedINTEL CORP·Filed 1996·Granted Dec 10, 1996·89 cites·8 claims
- 1879US9612836B2System, method, and computer program product for implementing software-based scoreboardingNVIDIA CORP·Filed 2014·Granted Apr 4, 2017·5 cites·19 claims
- 1979US5768576AMethod and apparatus for predicting and handling resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1996·Granted Jun 16, 1998·75 cites·19 claims
- 2078US10095548B2Mechanism for waking common resource requests within a resource management subsystemFETTERMAN MICHAEL·Filed 2012·Granted Oct 9, 2018·5 cites·21 claims
- 2178US7941651B1Method and apparatus for combining micro-operations to process immediate dataINTEL CORP·Filed 2002·Granted May 10, 2011·26 cites·16 claims
- 2278US7500049B2Providing a backing store in user-level memoryINTEL CORP·Filed 2005·Granted Mar 3, 2009·8 cites·26 claims
- 2378US5687338AMethod and apparatus for maintaining a macro instruction for refetching in a pipelined processorINTEL CORP·Filed 1995·Granted Nov 11, 1997·81 cites·6 claims
- 2477US9477482B2System, method, and computer program product for implementing multi-cycle register file bypassNVIDIA CORP·Filed 2013·Granted Oct 25, 2016·4 cites·20 claims
- 2577US2024378792A1Transcoding compressed texture sets to textures with a hardware-supported compression formatNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2677US2024378759A1Decompression of compressed texture setsNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2776US11379944B2Techniques for performing accelerated point sampling in a texture processing pipelineNVIDIA CORP·Filed 2020·Granted Jul 5, 2022·1 cites·20 claims
- 2876US5809271AMethod and apparatus for changing flow of control in a processorINTEL CORP·Filed 1995·Granted Sep 15, 1998·63 cites·7 claims
- 2976US5729728AMethod and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessorINTEL CORP·Filed 1996·Granted Mar 17, 1998·67 cites·49 claims
- 3076US5561814AMethods and apparatus for determining memory operating characteristics for given memory locations via assigned address rangesINTEL CORP·Filed 1993·Granted Oct 1, 1996·59 cites·38 claims
- 3175US7404065B2Flow optimization and prediction for VSSE memory operationsINTEL CORP·Filed 2005·Granted Jul 22, 2008·7 cites·23 claims
- 3275US5463745AMethods and apparatus for determining the next instruction pointer in an out-of-order execution computer systemINTEL CORP·Filed 1993·Granted Oct 31, 1995·66 cites·22 claims
- 3375US5452426ACoordinating speculative and committed state register source data and immediate source data in a processorINTEL CORP·Filed 1994·Granted Sep 19, 1995·66 cites·44 claims
- 3474US11768686B2Out of order memory request tracking structure and techniqueNVIDIA CORP·Filed 2020·Granted Sep 26, 2023·1 cites·36 claims
- 3573US10067768B2Execution of divergent threads using a convergence barrierNVIDIA CORP·Filed 2015·Granted Sep 4, 2018·2 cites·20 claims
- 3672US8239659B2Vector completion mask handlingJOURDAN STEPHAN·Filed 2006·Granted Aug 7, 2012·6 cites·22 claims
- 3771US5809325ACircuit and method for scheduling instructions by predicting future availability of resources required for executionINTEL CORP·Filed 1996·Granted Sep 15, 1998·44 cites·8 claims
- 3870US5974523AMechanism for efficiently overlapping multiple operand types in a microprocessorINTEL CORP·Filed 1996·Granted Oct 26, 1999·40 cites·27 claims
- 3970US5546597AReady selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction executionINTEL CORP·Filed 1994·Granted Aug 13, 1996·51 cites·22 claims
- 4068US5903751AMethod and apparatus for implementing a branch target buffer in CISC processorINTEL CORP·Filed 1997·Granted May 11, 1999·38 cites·3 claims
- 4168US5564056AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1994·Granted Oct 8, 1996·41 cites·10 claims
- 4268US5564111AMethod and apparatus for implementing a non-blocking translation lookaside bufferINTEL CORP·Filed 1994·Granted Oct 8, 1996·46 cites·18 claims
- 4367US6393550B1Method and apparatus for pipeline streamlining where resources are immediate or certainly retiredINTEL CORP·Filed 1995·Granted May 21, 2002·50 cites·20 claims
- 4465US5951670ASegment register renaming in an out of order processorINTEL CORP·Filed 1997·Granted Sep 14, 1999·47 cites·1 claims
- 4565US5664137AMethod and apparatus for executing and dispatching store operations in a computer systemINTEL CORP·Filed 1995·Granted Sep 2, 1997·52 cites·49 claims
- 4665US5574942AHybrid execution unit for complex microprocessorINTEL CORP·Filed 1996·Granted Nov 12, 1996·54 cites·29 claims
- 4765US5553256AApparatus for pipeline streamlining where resources are immediate or certainly retiredINTEL CORP·Filed 1995·Granted Sep 3, 1996·49 cites·5 claims
- 4863US11823318B2Techniques for interleaving texturesNVIDIA CORP·Filed 2021·Granted Nov 21, 2023·0 cites·17 claims
- 4963US5615385AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1995·Granted Mar 25, 1997·37 cites·6 claims
- 5062US5778407AMethods and apparatus for determining operating characteristics of a memory element based on its physical locationINTEL CORP·Filed 1996·Granted Jul 7, 1998·35 cites·7 claims
Showing the top 50 of 81 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →