Inventor · disambiguated record
Jedrzej Solecki
Also filed as: SOLECKI JEDRZEJ
9 granted patents·19 citations·filing 2013–2020
83Inventor score
Files withMENTOR GRAPHICS CORP9
Top patents by PatentIndex Score
9 records- 0187US9003248B2Fault-driven scan chain configuration for test-per-clockMENTOR GRAPHICS CORP·Filed 2013·Granted Apr 7, 2015·6 cites·16 claims
- 0283US9714981B2Test-per-clock based on dynamically-partitioned reconfigurable scan chainsMENTOR GRAPHICS CORP·Filed 2016·Granted Jul 25, 2017·2 cites·20 claims
- 0380US9335377B2Test-per-clock based on dynamically-partitioned reconfigurable scan chainsMENTOR GRAPHICS CORP·Filed 2013·Granted May 10, 2016·3 cites·10 claims
- 0479US9933485B2Deterministic built-in self-test based on compressed test patterns stored on chip and their derivativesMENTOR GRAPHICS CORP·Filed 2016·Granted Apr 3, 2018·2 cites·20 claims
- 0578US10963612B2Scan cell architecture for improving test coverage and reducing test application timeMENTOR GRAPHICS CORP·Filed 2020·Granted Mar 30, 2021·1 cites·14 claims
- 0675US9347993B2Test generation for test-per-clockMENTOR GRAPHICS CORP·Filed 2013·Granted May 24, 2016·3 cites·18 claims
- 0763US9009553B2Scan chain configuration for test-per-clock based on circuit topologyMENTOR GRAPHICS CORP·Filed 2013·Granted Apr 14, 2015·1 cites·14 claims
- 0862US10379161B2Scan chain stitching for test-per-clockMENTOR GRAPHICS CORP·Filed 2013·Granted Aug 13, 2019·1 cites·20 claims
- 0943US10509072B2Test application time reduction using capture-per-cycle test pointsMENTOR GRAPHICS CORP·Filed 2018·Granted Dec 17, 2019·0 cites·14 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →