Inventor · disambiguated record
Klaus J. Getzlaff
Also filed as: GETZLAFF KLAUS · GETZLAFF KLAUS J · GETZLAFF KLAUS JOERG · GETZLAFF KLAUS JORG
21 granted patents·498 citations·filing 1980–1998
96Inventor score
Files withIBM21
Top patents by PatentIndex Score
21 records- 0189US5473574AMulti-port static random access memory with fast write-thru schemeIBM·Filed 1993·Granted Dec 5, 1995·79 cites·14 claims
- 0274US6014756AHigh availability error self-recovering shared cache for multiprocessor systemsIBM·Filed 1995·Granted Jan 11, 2000·96 cites·12 claims
- 0372US5594876AArbitration protocol for a bidirectional bus for handling access requests to a logically divided memory in a multiprocessor systemIBM·Filed 1995·Granted Jan 14, 1997·73 cites·9 claims
- 0460US4631663AMacroinstruction execution in a microprogram-controlled processorIBM·Filed 1983·Granted Dec 23, 1986·29 cites·7 claims
- 0554US5996063AManagement of both renamed and architected registers in a superscalar computer systemIBM·Filed 1997·Granted Nov 30, 1999·28 cites·13 claims
- 0653US4656578ADevice in the instruction unit of a pipeline processor for instruction interruption and repetitionIBM·Filed 1984·Granted Apr 7, 1987·19 cites·5 claims
- 0752US6108771ARegister renaming with a pool of physical registersIBM·Filed 1998·Granted Aug 22, 2000·26 cites·7 claims
- 0851US5311519AMultiplexerIBM·Filed 1992·Granted May 10, 1994·15 cites·12 claims
- 0948US6237076B1Method for register renaming by copying a 32 bits instruction directly or indirectly to a 64 bits instructionIBM·Filed 1998·Granted May 22, 2001·22 cites·3 claims
- 1046US5964845AProcessing system having improved bi-directional serial clock communication circuitryIBM·Filed 1995·Granted Oct 12, 1999·18 cites·11 claims
- 1144US5303365AClock generation in a multi-chip computer systemIBM·Filed 1991·Granted Apr 12, 1994·8 cites·6 claims
- 1243US5754875AComputer system with double width data busIBM·Filed 1996·Granted May 19, 1998·19 cites·16 claims
- 1342US5870601AData processing apparatus and method for correcting faulty microcode in a ROM device via a flag microinstruction in a RAM device including corrected microcodeIBM·Filed 1995·Granted Feb 9, 1999·18 cites·8 claims
- 1442US5138707AMethod of operating a timer in a digital data processing systemIBM·Filed 1989·Granted Aug 11, 1992·12 cites·12 claims
- 1533US5889969ALogical bus structure including plural physical busses for a multiprocessor system with a multi-level cache memory structureIBM·Filed 1995·Granted Mar 30, 1999·10 cites·12 claims
- 1633US5875123ACarry-select adder with pre-counting of leading zero digitsIBM·Filed 1995·Granted Feb 23, 1999·6 cites·17 claims
- 1733US5070471AHigh speed multiplier which divides multiplying factor into parts and adds partial end productsIBM·Filed 1990·Granted Dec 3, 1991·8 cites·17 claims
- 1831US5978957AVery fast pipelined shifter element with parity predictionIBM·Filed 1995·Granted Nov 2, 1999·3 cites·20 claims
- 1930US6275839B1Method and system for immediate exponent normalization in a fast floating point adderIBM·Filed 1998·Granted Aug 14, 2001·2 cites·8 claims
- 2030US4398247AControl device for directing execution of forced operations in a data processing systemIBM·Filed 1980·Granted Aug 9, 1983·6 cites·6 claims
- 2125US4400776AData processor control subsystemIBM·Filed 1980·Granted Aug 23, 1983·1 cites·5 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →