Inventor · disambiguated record
Charles M. Flaig
Also filed as: FLAIG CHARLES M
11 granted patents·558 citations·filing 1988–1999
92Inventor score
Top patents by PatentIndex Score
11 records- 0197US5105424AInter-computer message routing system with each computer having separate routinng automata for each dimension of the networkCALIFORNIA INST OF TECHN·Filed 1988·Granted Apr 14, 1992·290 cites·26 claims
- 0283US5802055AMethod and apparatus for dynamic buffer allocation in a bus bridge for pipelined readsAPPLE COMPUTER·Filed 1996·Granted Sep 1, 1998·118 cites·29 claims
- 0363US5674077AInterleaved connector circuit having increased backplane impedanceAPPLE COMPUTER·Filed 1994·Granted Oct 7, 1997·24 cites·13 claims
- 0456US5473762AMethod and system for pipelining bus requestsAPPLE COMPUTER·Filed 1994·Granted Dec 5, 1995·28 cites·8 claims
- 0552US5410677AApparatus for translating data formats starting at an arbitrary byte positionAPPLE COMPUTER·Filed 1991·Granted Apr 25, 1995·24 cites·21 claims
- 0645US5630077ASystem and method for coordinating access to a busAPPLE COMPUTER·Filed 1996·Granted May 13, 1997·17 cites·10 claims
- 0742US5748917ALine data architecture and bus interface circuits and methods for dual-edge clocking of data to bus-linked limited capacity devicesAPPLE COMPUTER·Filed 1995·Granted May 5, 1998·15 cites·3 claims
- 0842US5692137AMaster oriented bus bridgeAPPLE COMPUTER·Filed 1995·Granted Nov 25, 1997·16 cites·4 claims
- 0941US5590130ABus protocol using separate clocks for arbitration and data transferAPPLE COMPUTER·Filed 1995·Granted Dec 31, 1996·13 cites·13 claims
- 1035US6867780B1System, method and article of manufacture for allowing direct memory access to graphics vertex data while bypassing a processorNVIDIA CORP·Filed 1999·Granted Mar 15, 2005·6 cites·27 claims
- 1135US5557755AMethod and system for improving bus utilization efficiencyAPPLE COMPUTER·Filed 1994·Granted Sep 17, 1996·7 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →