Inventor · disambiguated record
David Jefferson
Also filed as: JEFFERSON DAVID · JEFFERSON DAVID E · JEFFERSON DAVID EDWARD
64 granted patents·2 pending applications·2,229 citations·filing 1992–2020
99Inventor score
Files withALTERA CORP59LANGHAMMER MARTIN2JOYCE JUJU1MICRON TECHNOLOGY INC1SAMSUNG SEMICONDUCTOR INC1
Top patents by PatentIndex Score
66 records- 0199US6215326B1Programmable logic device architecture with super-regions having logic regions and a memory regionALTERA CORP·Filed 1999·Granted Apr 10, 2001·331 cites·20 claims
- 0299US5744991ASystem for distributing clocks using a delay lock loop in a programmable logic circuitALTERA CORP·Filed 1995·Granted Apr 28, 1998·216 cites·6 claims
- 0398US6292016B1Programmable logic with on-chip DLL or PLL to distribute clockALTERA CORP·Filed 2000·Granted Sep 18, 2001·93 cites·38 claims
- 0498US5963069ASystem for distributing clocks using a delay lock loop in a programmable logic circuitALTERA CORP·Filed 1997·Granted Oct 5, 1999·142 cites·23 claims
- 0597US6130552AProgrammable logic integrated circuit with on-chip DLL or PLL for clock distributionALTERA CORP·Filed 1998·Granted Oct 10, 2000·105 cites·51 claims
- 0696US7725738B1FPGA configuration bitstream protection using multiple keysALTERA CORP·Filed 2005·Granted May 25, 2010·52 cites·19 claims
- 0796US7606362B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2005·Granted Oct 20, 2009·40 cites·20 claims
- 0896US6326812B1Programmable logic device with logic signal delay compensated clock networkALTERA CORP·Filed 2000·Granted Dec 4, 2001·64 cites·16 claims
- 0996US6107820ARedundancy circuitry for programmable logic devices with interleaved input circuitsALTERA CORP·Filed 1998·Granted Aug 22, 2000·101 cites·18 claims
- 1095US5850152AProgrammable logic array integrated circuit devicesALTERA CORP·Filed 1997·Granted Dec 15, 1998·69 cites·10 claims
- 1194US5642082ALoop filter level detection circuit and methodALTERA CORP·Filed 1996·Granted Jun 24, 1997·105 cites·19 claims
- 1293US7818584B1One-time programmable memories for key storageALTERA CORP·Filed 2005·Granted Oct 19, 2010·29 cites·14 claims
- 1393US6417694B1Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2001·Granted Jul 9, 2002·40 cites·9 claims
- 1493US5977793AProgrammable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 1997·Granted Nov 2, 1999·87 cites·43 claims
- 1592US7734043B1Encryption key obfuscation and storageALTERA CORP·Filed 2005·Granted Jun 8, 2010·31 cites·19 claims
- 1692US5850151AProgrammable logic array intergrated circuit devicesALTERA CORP·Filed 1997·Granted Dec 15, 1998·47 cites·16 claims
- 1792US5847617AVariable-path-length voltage-controlled oscillator circuitALTERA CORP·Filed 1997·Granted Dec 8, 1998·91 cites·12 claims
- 1890US6965249B2Programmable logic device with redundant circuitryALTERA CORP·Filed 2002·Granted Nov 15, 2005·39 cites·109 claims
- 1989US8363833B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2011·Granted Jan 29, 2013·8 cites·23 claims
- 2087US9208357B1FPGA configuration bitstream protection using multiple keysALTERA CORP·Filed 2014·Granted Dec 8, 2015·6 cites·18 claims
- 2186US9054859B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2014·Granted Jun 9, 2015·5 cites·20 claims
- 2286US6300794B1Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2000·Granted Oct 9, 2001·23 cites·20 claims
- 2385US6577160B2Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2002·Granted Jun 10, 2003·21 cites·12 claims
- 2485US5699020APhase latched differential charge pump circuit and methodALTERA CORP·Filed 1996·Granted Dec 16, 1997·85 cites·8 claims
- 2584US7228451B1Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuitALTERA CORP·Filed 2005·Granted Jun 5, 2007·12 cites·20 claims
- 2684US6657456B1Programmable logic with on-chip DLL or PLL to distribute clockALTERA CORP·Filed 2001·Granted Dec 2, 2003·18 cites·17 claims
- 2781US6163195ATemperature compensated delay chainALTERA CORP·Filed 1999·Granted Dec 19, 2000·38 cites·31 claims
- 2880US7984292B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2009·Granted Jul 19, 2011·5 cites·20 claims
- 2979US6337578B2Redundancy circuitry for programmable logic devices with interleaved input circuitsALTERA CORP·Filed 2001·Granted Jan 8, 2002·16 cites·25 claims
- 3077US8209545B1FPGA configuration bitstream protection using multiple keysLANGHAMMER MARTIN·Filed 2010·Granted Jun 26, 2012·3 cites·14 claims
- 3176US6826741B1Flexible I/O routing resourcesALTERA CORP·Filed 2002·Granted Nov 30, 2004·18 cites·27 claims
- 3276US6392438B1Programmable logic array integrated circuit devicesALTERA CORP·Filed 2000·Granted May 21, 2002·10 cites·20 claims
- 3376US6222382B1Redundancy circuitry for programmable logic devices with interleaved input circuitsALTERA CORP·Filed 2000·Granted Apr 24, 2001·14 cites·17 claims
- 3474US6127865AProgrammable logic device with logic signal delay compensated clock networkALTERA CORP·Filed 1998·Granted Oct 3, 2000·57 cites·28 claims
- 3573US7236411B1Programmable memory access parametersALTERA CORP·Filed 2005·Granted Jun 26, 2007·9 cites·29 claims
- 3671US6262933B1High speed programmable address decoderALTERA CORP·Filed 2000·Granted Jul 17, 2001·16 cites·17 claims
- 3769US8750503B1FPGA configuration bitstream encryption using modified keyALTERA CORP·Filed 2013·Granted Jun 10, 2014·1 cites·20 claims
- 3869US6600337B2Line segmentation in programmable logic devices having redundancy circuitryALTERA CORP·Filed 2001·Granted Jul 29, 2003·16 cites·20 claims
- 3968US7051153B1Memory array operating as a shift registerALTERA CORP·Filed 2002·Granted May 23, 2006·16 cites·22 claims
- 4068US6996736B1Programmable clock network for distributing clock signals to and between first and second sections of an integrated circuitALTERA CORP·Filed 2002·Granted Feb 7, 2006·12 cites·17 claims
- 4167US8826038B1FPGA configuration bitstream protection using multiple keysLANGHAMMER MARTIN·Filed 2012·Granted Sep 2, 2014·1 cites·18 claims
- 4267US6107825AInput/output circuitry for programmable logic devicesALTERA CORP·Filed 1998·Granted Aug 22, 2000·18 cites·15 claims
- 4365US6759871B2Line segmentation in programmable logic devices having redundancy circuitryALTERA CORP·Filed 2003·Granted Jul 6, 2004·10 cites·20 claims
- 4460US7343470B1Techniques for sequentially transferring data from a memory device through a parallel interfaceALTERA CORP·Filed 2003·Granted Mar 11, 2008·8 cites·20 claims
- 4560US6798242B2Programmable logic device with hierarchical interconnection resourcesALTERA CORP·Filed 2003·Granted Sep 28, 2004·6 cites·4 claims
- 4660US6115312AProgrammable logic device memory cell circuitALTERA CORP·Filed 1998·Granted Sep 5, 2000·19 cites·15 claims
- 4758US7397726B1Flexible RAM clock enableALTERA CORP·Filed 2006·Granted Jul 8, 2008·3 cites·21 claims
- 4858US5293623ARandom access memory based buffer memory and associated method utilizing pipelined look-ahead readingSAMSUNG SEMICONDUCTOR INC·Filed 1992·Granted Mar 8, 1994·38 cites·17 claims
- 4957US6480028B2Programmable logic device architectures with super-regions having logic regions and memory regionALTERA CORP·Filed 2002·Granted Nov 12, 2002·5 cites·19 claims
- 5054US6720796B1Multiple size memories in a programmable logic deviceALTERA CORP·Filed 2002·Granted Apr 13, 2004·5 cites·16 claims
Showing the top 50 of 66 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →