Inventor · disambiguated record

Nitesh Naidu

Also filed as: NAIDU NITESH

3 granted patents·5 citations·filing 2022–2024

55Inventor score

Technology areasH03L

Files withSHAOXING YUANFANG SEMICONDUCTOR CO LTD3

Top patents by PatentIndex Score

3 records

0190US11588489B1Obtaining lock in a phase-locked loop (PLL) upon being out of phase-lockSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Feb 21, 2023·5 cites·20 claims
0266US12149255B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2024·Granted Nov 19, 2024·0 cites·6 claims
0358US11967965B2Generating divided signals from phase-locked loop (PLL) output when reference clock is unavailableSHAOXING YUANFANG SEMICONDUCTOR CO LTD·Filed 2022·Granted Apr 23, 2024·0 cites·13 claims

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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →