Inventor · disambiguated record
Derek T. Bachand
Also filed as: BACHAND DEREK · BACHAND DEREK T
30 granted patents·1 pending application·601 citations·filing 1997–2020
97Inventor score
Files withINTEL CORP24MICROSOFT TECHNOLOGY LICENSING LLC4HILL DAVID L1PRUDVI CHINNA1SAFRANEK ROBERT J1
Top patents by PatentIndex Score
31 records- 0197US7487305B2Prioritized bus request scheduling mechanism for processing devicesINTEL CORP·Filed 2006·Granted Feb 3, 2009·50 cites·20 claims
- 0290US6732242B2External bus transaction scheduling systemINTEL CORP·Filed 2002·Granted May 4, 2004·63 cites·26 claims
- 0389US6668309B2Snoop blocking for cache coherencyINTEL CORP·Filed 2003·Granted Dec 23, 2003·48 cites·11 claims
- 0487US6782457B2Prioritized bus request scheduling mechanism for processing devicesINTEL CORP·Filed 2003·Granted Aug 24, 2004·33 cites·13 claims
- 0586US6606692B2Prioritized bus request scheduling mechanism for processing devicesINTEL CORP·Filed 2002·Granted Aug 12, 2003·29 cites·19 claims
- 0686US6499090B1Prioritized bus request scheduling mechanism for processing devicesINTEL CORP·Filed 1999·Granted Dec 24, 2002·80 cites·19 claims
- 0776US6578116B2Snoop blocking for cache coherencyINTEL CORP·Filed 2002·Granted Jun 10, 2003·18 cites·10 claims
- 0875US6321297B1Avoiding tag compares during writes in multi-level cache hierarchyINTEL CORP·Filed 1998·Granted Nov 20, 2001·80 cites·17 claims
- 0969US7133981B2Prioritized bus request scheduling mechanism for processing devicesINTEL CORP·Filed 2004·Granted Nov 7, 2006·8 cites·24 claims
- 1068US8205111B2Communicating via an in-die interconnectHILL DAVID L·Filed 2009·Granted Jun 19, 2012·4 cites·18 claims
- 1168US6735675B2Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 2003·Granted May 11, 2004·10 cites·18 claims
- 1266US6578114B2Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 2002·Granted Jun 10, 2003·9 cites·36 claims
- 1365US7143242B2Dynamic priority external transaction systemINTEL CORP·Filed 2003·Granted Nov 28, 2006·8 cites·31 claims
- 1461US6216208B1Prefetch queue responsive to read request sequencesINTEL CORP·Filed 1997·Granted Apr 10, 2001·39 cites·14 claims
- 1559US6078981ATransaction stall technique to prevent livelock in multiple-processor systemsINTEL CORP·Filed 1997·Granted Jun 20, 2000·33 cites·15 claims
- 1654US6378048B1“SLIME” cache coherency system for agents with multi-layer cachesINTEL CORP·Filed 1998·Granted Apr 23, 2002·29 cites·23 claims
- 1753US10133670B2Low overhead hierarchical connectivity of cache coherent agents to a coherent fabricINTEL CORP·Filed 2014·Granted Nov 20, 2018·0 cites·14 claims
- 1852US11354239B2Maintaining domain coherence states including domain state no-owned (DSN) in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jun 7, 2022·0 cites·30 claims
- 1951US11138114B2Providing dynamic selection of cache coherence protocols in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Oct 5, 2021·0 cites·36 claims
- 2051US11093396B2Enabling atomic memory accesses across coherence granule boundaries in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2019·Granted Aug 17, 2021·0 cites·23 claims
- 2148US8122194B2Transaction manager and cache for processing agentPRUDVI CHINNA·Filed 2009·Granted Feb 21, 2012·0 cites·16 claims
- 2248US6434677B1Method and apparatus for altering data length to zero to maintain cache coherencyINTEL CORP·Filed 1999·Granted Aug 13, 2002·15 cites·15 claims
- 2347US11372757B2Tracking repeated reads to guide dynamic selection of cache coherence protocols in processor-based devicesMICROSOFT TECHNOLOGY LICENSING LLC·Filed 2020·Granted Jun 28, 2022·0 cites·24 claims
- 2446US6412091B2Error correction system in a processing agent having minimal delayINTEL CORP·Filed 2001·Granted Jun 25, 2002·3 cites·19 claims
- 2543US6460119B1Snoop blocking for cache coherencyINTEL CORP·Filed 1998·Granted Oct 1, 2002·11 cites·14 claims
- 2641US6654837B1Dynamic priority external transaction systemINTEL CORP·Filed 1999·Granted Nov 25, 2003·10 cites·12 claims
- 2741US6209068B1Read line buffer and signaling protocol for processorINTEL CORP·Filed 1997·Granted Mar 27, 2001·12 cites·12 claims
- 2841US2007073977A1Early global observation point for a uniprocessor systemSAFRANEK ROBERT J·Filed 2005·Application pending·0 cites
- 2934US6401172B1Recycle mechanism for a processing agentINTEL CORP·Filed 1998·Granted Jun 4, 2002·6 cites·11 claims
- 3032US6269465B1Error correction system in a processing agent having minimal delayINTEL CORP·Filed 1998·Granted Jul 31, 2001·2 cites·23 claims
- 3130US7555603B1Transaction manager and cache for processing agentINTEL CORP·Filed 1998·Granted Jun 30, 2009·1 cites·15 claims
Join the waitlist — get patent alerts
Get an alert when Derek T. Bachand files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →