Inventor · disambiguated record
Mitesh Agrawal
Also filed as: AGRAWAL MITESH · AGRAWAL MITESH A
11 granted patents·1 pending application·23 citations·filing 2011–2025
86Inventor score
Top patents by PatentIndex Score
12 records- 0184US10365132B2Methods and systems for performing test and calibration of integrated sensorsIBM·Filed 2018·Granted Jul 30, 2019·2 cites·7 claims
- 0280US8832626B2Distributing spare latch circuits in integrated circuit designsIBM·Filed 2013·Granted Sep 9, 2014·7 cites·12 claims
- 0378US10026498B1Simultaneous scan chain initialization with disparate latchesIBM·Filed 2017·Granted Jul 17, 2018·3 cites·17 claims
- 0476US8490039B2Distributing spare latch circuits in integrated circuit designsAGRAWAL MITESH A·Filed 2011·Granted Jul 16, 2013·7 cites·15 claims
- 0575US10199121B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2018·Granted Feb 5, 2019·2 cites·2 claims
- 0675US2025388231A1Method and system for feasibility-based operation of an autonomous agentMAY MOBILITY INC·Filed 2025·Application pending·0 cites
- 0773US10096377B1Simultaneous scan chain initialization with disparate latchesIBM·Filed 2017·Granted Oct 9, 2018·2 cites·1 claims
- 0870US12296849B2Method and system for feasibility-based operation of an autonomous agentMAY MOBILITY INC·Filed 2022·Granted May 13, 2025·0 cites·18 claims
- 0957US10598526B2Methods and systems for performing test and calibration of integrated sensorsIBM·Filed 2016·Granted Mar 24, 2020·0 cites·12 claims
- 1054US10658062B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2019·Granted May 19, 2020·0 cites·8 claims
- 1153US10586606B2Simultaneous scan chain initialization with disparate latchesIBM·Filed 2019·Granted Mar 10, 2020·0 cites·17 claims
- 1244US10571519B2Performing system functional test on a chip having partial-good portionsIBM·Filed 2016·Granted Feb 25, 2020·0 cites·11 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →