Inventor · disambiguated record
Robert B. Tremaine
Also filed as: TREMAINE ROBERT B · TREMAINE ROBERT BRETT
73 granted patents·6 pending applications·1,112 citations·filing 2000–2013
99Inventor score
Top patents by PatentIndex Score
79 records- 0198US9300298B2Programmable logic circuit using three-dimensional stacking techniquesIBM·Filed 2013·Granted Mar 29, 2016·29 cites·9 claims
- 0297US8516409B2Implementing vertical die stacking to distribute logical function over multiple dies in through-silicon-via stacked semiconductor deviceCOTEUS PAUL W·Filed 2010·Granted Aug 20, 2013·41 cites·4 claims
- 0397US7587559B2Systems and methods for memory module power managementIBM·Filed 2006·Granted Sep 8, 2009·63 cites·28 claims
- 0495US7984329B2System and method for providing DRAM device-level repair via address remappings external to the deviceIBM·Filed 2007·Granted Jul 19, 2011·41 cites·22 claims
- 0595US7913041B2Cache reconfiguration based on analyzing one or more characteristics of run-time performance data or software hintIBM·Filed 2008·Granted Mar 22, 2011·38 cites·16 claims
- 0695US7584336B2Systems and methods for providing data modification operations in memory subsystemsIBM·Filed 2006·Granted Sep 1, 2009·47 cites·33 claims
- 0795US6339813B1Memory system for permitting simultaneous processor access to a cache line and sub-cache line sectors fill and writeback to a system memoryIBM·Filed 2000·Granted Jan 15, 2002·124 cites·26 claims
- 0892US7594055B2Systems and methods for providing distributed technology independent memory controllersIBM·Filed 2006·Granted Sep 22, 2009·30 cites·31 claims
- 0991US8692561B2Implementing chip to chip calibration within a TSV stackCORDERO EDGAR R·Filed 2011·Granted Apr 8, 2014·15 cites·20 claims
- 1090US7539842B2Computer memory system for selecting memory buses according to physical memory organization information stored in virtual address translation tablesIBM·Filed 2006·Granted May 26, 2009·19 cites·13 claims
- 1190US6446145B1Computer memory compression abort and bypass mechanism when cache write back buffer is fullIBM·Filed 2000·Granted Sep 3, 2002·74 cites·21 claims
- 1289US9798528B2Software solution for cooperative memory-side and processor-side data prefetchingGAO YAOQING·Filed 2006·Granted Oct 24, 2017·25 cites·22 claims
- 1389US9086957B2Requesting a memory space by a memory controllerCORDERO EDGAR R·Filed 2012·Granted Jul 21, 2015·17 cites·19 claims
- 1489US8618960B1Selective recompression of a string compressed by a plurality of diverse lossless compression techniquesAGARWAL KANAK B·Filed 2012·Granted Dec 31, 2013·10 cites·14 claims
- 1589US8493089B2Programmable logic circuit using three-dimensional stacking techniquesCORDERO EDGAR R·Filed 2011·Granted Jul 23, 2013·8 cites·12 claims
- 1689US7636813B2Systems and methods for providing remote pre-fetch buffersIBM·Filed 2006·Granted Dec 22, 2009·21 cites·17 claims
- 1788US7636833B2Method for selecting memory busses according to physical memory organization information associated with virtual address translation tablesIBM·Filed 2009·Granted Dec 22, 2009·15 cites·6 claims
- 1888US6851030B2System and method for dynamically allocating associative resourcesIBM·Filed 2002·Granted Feb 1, 2005·55 cites·32 claims
- 1987US8495318B2Memory page management in a tiered memory systemTREMAINE ROBERT B·Filed 2010·Granted Jul 23, 2013·11 cites·24 claims
- 2087US8140764B2System for reconfiguring cache memory having an access bit associated with a sector of a lower-level cache memory and a granularity bit associated with a sector of a higher-level cache memorySHEN XIAOWEI·Filed 2011·Granted Mar 20, 2012·9 cites·3 claims
- 2187US6549995B1Compressor system memory organization and method for low latency access to uncompressed memory regionsIBM·Filed 2000·Granted Apr 15, 2003·53 cites·19 claims
- 2286US6766429B1Low cost and high RAS mirrored memoryIBM·Filed 2000·Granted Jul 20, 2004·42 cites·15 claims
- 2385US7277988B2System, method and storage medium for providing data caching and data compression in a memory subsystemIBM·Filed 2004·Granted Oct 2, 2007·30 cites·15 claims
- 2484US6775751B2System and method for using a compressed main memory based on degree of compressibilityIBM·Filed 2002·Granted Aug 10, 2004·38 cites·27 claims
- 2583US7581073B2Systems and methods for providing distributed autonomous power management in a memory systemIBM·Filed 2006·Granted Aug 25, 2009·12 cites·29 claims
- 2683US7287138B2Low cost and high RAS mirrored memoryIBM·Filed 2004·Granted Oct 23, 2007·29 cites·4 claims
- 2783US6901483B2Prioritizing and locking removed and subsequently reloaded cache linesIBM·Filed 2002·Granted May 31, 2005·36 cites·20 claims
- 2882US8230422B2Assist thread for injecting cache memory in a microprocessorBOHRER PATRICK JOSEPH·Filed 2005·Granted Jul 24, 2012·12 cites·25 claims
- 2982US7640386B2Systems and methods for providing memory modules with multiple hub devicesIBM·Filed 2006·Granted Dec 29, 2009·11 cites·20 claims
- 3081US9384108B2Functional built-in self test for a chipIBM·Filed 2012·Granted Jul 5, 2016·6 cites·20 claims
- 3181US8051276B2Operating system thread scheduling for optimal heat dissipationIBM·Filed 2006·Granted Nov 1, 2011·11 cites·19 claims
- 3280US8495328B2Providing frame start indication in a memory system having indeterminate read data latencyCOTEUS PAUL W·Filed 2012·Granted Jul 23, 2013·3 cites·10 claims
- 3380US8490065B2Method and apparatus for software-assisted data cache and prefetch controlARCHAMBAULT ROCH·Filed 2005·Granted Jul 16, 2013·14 cites·20 claims
- 3480US8219746B2Memory package utilizing at least two types of memoriesTREMAINE ROBERT B·Filed 2009·Granted Jul 10, 2012·8 cites·19 claims
- 3580US7437517B2Methods and arrangements to manage on-chip memory to reduce memory latencyIBM·Filed 2005·Granted Oct 14, 2008·9 cites·9 claims
- 3678US8674856B2Data compression utilizing longest common subsequence templateAGARWAL KANAK B·Filed 2012·Granted Mar 18, 2014·5 cites·16 claims
- 3776US8595463B2Memory architecture with policy based data storageTREMAINE ROBERT B·Filed 2010·Granted Nov 26, 2013·4 cites·20 claims
- 3876US7490217B2Design structure for selecting memory busses according to physical memory organization information stored in virtual address translation tablesIBM·Filed 2008·Granted Feb 10, 2009·7 cites·17 claims
- 3975US8806177B2Prefetch engine based translation prefetchingKRIEGER ORRAN Y·Filed 2006·Granted Aug 12, 2014·8 cites·20 claims
- 4075US7685392B2Providing indeterminate read data latency in a memory systemIBM·Filed 2005·Granted Mar 23, 2010·4 cites·25 claims
- 4172US8869153B2Quality of service scheduling for simultaneous multi-threaded processorsKRIEGER ORRAN Y·Filed 2008·Granted Oct 21, 2014·5 cites·19 claims
- 4272US8493801B2Strobe offset in bidirectional memory strobe configurationsDREPS DANIEL M·Filed 2012·Granted Jul 23, 2013·4 cites·7 claims
- 4372US8145868B2Method and system for providing frame start indication in a memory system having indeterminate read data latencyCOTEUS PAUL W·Filed 2007·Granted Mar 27, 2012·3 cites·8 claims
- 4471US8284621B2Strobe offset in bidirectional memory strobe configurationsDREPS DANIEL M·Filed 2010·Granted Oct 9, 2012·4 cites·7 claims
- 4571US7447831B2Memory systems for automated computing machineryIBM·Filed 2006·Granted Nov 4, 2008·4 cites·15 claims
- 4670US8850115B2Memory package utilizing at least two types of memoriesTREMAINE ROBERT B·Filed 2012·Granted Sep 30, 2014·2 cites·20 claims
- 4769US7962700B2Systems and methods for reducing latency for accessing compressed memory using stratified compressed memory architectures and organizationIBM·Filed 2006·Granted Jun 14, 2011·4 cites·28 claims
- 4869US7610541B2Computer compressed memory system and method for storing and retrieving data in a processing systemIBM·Filed 2006·Granted Oct 27, 2009·4 cites·17 claims
- 4969US6665787B2Very high speed page operations in indirect accessed memory systemsIBM·Filed 2001·Granted Dec 16, 2003·15 cites·35 claims
- 5068US8949837B2Assist thread for injecting cache memory in a microprocessorBOHRER PATRICK JOSEPH·Filed 2012·Granted Feb 3, 2015·2 cites·22 claims
Showing the top 50 of 79 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →