Inventor · disambiguated record
Fung Fung Lee
Also filed as: LEE FUNG · LEE FUNG F · LEE FUNG FUNG
24 granted patents·1,108 citations·filing 1995–2017
97Inventor score
Top patents by PatentIndex Score
24 records- 0197US5909126AProgrammable logic array integrated circuit devices with interleaved logic array blocksALTERA CORP·Filed 1996·Granted Jun 1, 1999·133 cites·43 claims
- 0295US5982195AProgrammable logic device architecturesALTERA CORP·Filed 1997·Granted Nov 9, 1999·114 cites·21 claims
- 0394US6467009B1Configurable processor system unitTRISCEND CORP·Filed 1998·Granted Oct 15, 2002·294 cites·109 claims
- 0494US5880597AInterleaved interconnect for programmable logic array devicesALTERA CORP·Filed 1996·Granted Mar 9, 1999·106 cites·43 claims
- 0590US5883850AProgrammable logic array integrated circuitsALTERA CORP·Filed 1996·Granted Mar 16, 1999·68 cites·26 claims
- 0687US6459646B1Bank-based configuration and reconfiguration for programmable logic in a system on a chipTRISCEND CORP·Filed 2000·Granted Oct 1, 2002·54 cites·18 claims
- 0787US5631576AProgrammable logic array integrated circuit devices with flexible carry chainsALTERA CORP·Filed 1995·Granted May 20, 1997·59 cites·5 claims
- 0885US6102964AFitting for incremental compilation of electronic designsALTERA CORP·Filed 1997·Granted Aug 15, 2000·63 cites·40 claims
- 0985US5844854AProgrammable logic device with two dimensional memory addressingALTERA CORP·Filed 1996·Granted Dec 1, 1998·58 cites·22 claims
- 1078US7685214B2Order-preserving encoding formats of floating-point decimal numbers for efficient value comparisonIBM·Filed 2005·Granted Mar 23, 2010·9 cites·16 claims
- 1176US5963049AProgrammable logic array integrated circuit architecturesALTERA CORP·Filed 1997·Granted Oct 5, 1999·24 cites·14 claims
- 1275US5672985AProgrammable logic array integrated circuits with carry and/or cascade ringsALTERA CORP·Filed 1995·Granted Sep 30, 1997·30 cites·3 claims
- 1365US7412669B1Generation of graphical design representation from a design specification data fileXILINX INC·Filed 2006·Granted Aug 12, 2008·4 cites·20 claims
- 1463US6367056B1Method for incremental timing analysisALTERA CORP·Filed 1999·Granted Apr 2, 2002·42 cites·37 claims
- 1554US8378712B2Integrated circuit with crosslinked interconnect networksAGATE LOGIC INC·Filed 2009·Granted Feb 19, 2013·2 cites·29 claims
- 1653US10901854B2Temporal logical transactionsIBM·Filed 2017·Granted Jan 26, 2021·0 cites·5 claims
- 1750US10896096B2Temporal logical transactionsIBM·Filed 2016·Granted Jan 19, 2021·0 cites·9 claims
- 1850US6301694B1Hierarchical circuit partitioning using sliding windowsALTERA CORP·Filed 1997·Granted Oct 9, 2001·24 cites·23 claims
- 1949US7719311B1Integrated circuit with improved logic cellsAGATE LOGIC BEIJING INC·Filed 2009·Granted May 18, 2010·1 cites·7 claims
- 2049US6212668B1Gain matrix for hierarchical circuit partitioningALTERA CORP·Filed 1997·Granted Apr 3, 2001·23 cites·27 claims
- 2143US7915917B2Integrated circuit with improved logic cellsAGATE LOGIC BEIJING INC·Filed 2010·Granted Mar 29, 2011·0 cites·9 claims
- 2243US7911228B2Integrated circuit with improved logic cellsAGATE LOGIC BEIJING INC·Filed 2010·Granted Mar 22, 2011·0 cites·11 claims
- 2341US7899797B2Package resolution mechanism for database systemsIBM·Filed 2003·Granted Mar 1, 2011·0 cites·15 claims
- 2436US6366121B2Programmable logic array integrated circuit architecturesALTERA CORP·Filed 2001·Granted Apr 2, 2002·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →