Inventor · disambiguated record
Thomas L. Jeremiah
Also filed as: JEREMIAH THOMAS L · JEREMIAH THOMAS LEO
20 granted patents·589 citations·filing 1976–2009
96Inventor score
Top patents by PatentIndex Score
20 records- 0190US5287467APipeline for removing and concurrently executing two or more branch instructions in synchronization with other instructions executing in the execution unitIBM·Filed 1991·Granted Feb 15, 1994·141 cites·19 claims
- 0285US8521982B2Load request scheduling in a cache hierarchyCARGNONI ROBERT A·Filed 2009·Granted Aug 27, 2013·26 cites·8 claims
- 0378US8347037B2Victim cache replacementIBM·Filed 2008·Granted Jan 1, 2013·8 cites·21 claims
- 0476US8117397B2Victim cache line selectionGUTHRIE GUY L·Filed 2008·Granted Feb 14, 2012·7 cites·19 claims
- 0576US5303356ASystem for issuing instructions for parallel execution subsequent to branch into a group of member instructions with compoundability in dictation tagIBM·Filed 1991·Granted Apr 12, 1994·72 cites·13 claims
- 0675US5504932ASystem for executing scalar instructions in parallel based on control bits appended by compounding decoderIBM·Filed 1995·Granted Apr 2, 1996·74 cites·13 claims
- 0775US4021655AOversized data detection hardware for data processors which store data at variable length destinationsIBM·Filed 1976·Granted May 3, 1977·42 cites·12 claims
- 0868US5446850ACross-cache-line compounding algorithm for scism processorsIBM·Filed 1994·Granted Aug 29, 1995·42 cites·5 claims
- 0968US5386531AComputer system accelerator for multi-word cross-boundary storage accessIBM·Filed 1991·Granted Jan 31, 1995·52 cites·23 claims
- 1065US8327073B2Empirically based dynamic control of acceptance of victim cache lateral castoutsGUTHRIE GUY L·Filed 2009·Granted Dec 4, 2012·3 cites·27 claims
- 1164US5909694AMultiway associative external microprocessor cacheIBM·Filed 1997·Granted Jun 1, 1999·42 cites·6 claims
- 1263US8327072B2Victim cache replacementGUTHRIE GUY L·Filed 2008·Granted Dec 4, 2012·2 cites·15 claims
- 1363US6829702B1Branch target cache and method for efficiently obtaining target path instructions for tight program loopsIBM·Filed 2000·Granted Dec 7, 2004·9 cites·18 claims
- 1454US5398321AMicrocode generation for a scalable compound instruction set machineIBM·Filed 1994·Granted Mar 14, 1995·27 cites·9 claims
- 1549US5940877ACache address generation with and without carry-inIBM·Filed 1997·Granted Aug 17, 1999·21 cites·26 claims
- 1644US7484052B2Distributed address arbitration scheme for symmetrical multiprocessor systemIBM·Filed 2005·Granted Jan 27, 2009·0 cites·10 claims
- 1741US8166246B2Chaining multiple smaller store queue entries for more efficient store queue usageGUTHRIE GUY LYNN·Filed 2008·Granted Apr 24, 2012·0 cites·13 claims
- 1841US5701430ACross-cache-line compounding algorithm for scism processorsIBM·Filed 1995·Granted Dec 23, 1997·11 cites·2 claims
- 1940US5039939ACalculating AC chip performance using the LSSD scan pathIBM·Filed 1988·Granted Aug 13, 1991·8 cites·9 claims
- 2022US4234955AParity for computer system having an array of external registersIBM·Filed 1979·Granted Nov 18, 1980·2 cites·15 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →