Inventor · disambiguated record
H. Bernhard Pogge
Also filed as: POGGE H B · POGGE H BERNHARD
37 granted patents·3 pending applications·2,877 citations·filing 1974–2008
98Inventor score
Files withIBM40
Top patents by PatentIndex Score
40 records- 0199US6599778B2Chip and wafer integration process using vertical connectionsIBM·Filed 2001·Granted Jul 29, 2003·495 cites·16 claims
- 0299US6355501B1Three-dimensional chip stacking assemblyIBM·Filed 2000·Granted Mar 12, 2002·802 cites·12 claims
- 0398US7354798B2Three-dimensional device fabrication methodIBM·Filed 2002·Granted Apr 8, 2008·285 cites·13 claims
- 0495US7344959B1Metal filled through via structure for providing vertical wafer-to-wafer interconnectionIBM·Filed 2006·Granted Mar 18, 2008·39 cites·19 claims
- 0595US6864165B1Method of fabricating integrated electronic chip with an interconnect deviceIBM·Filed 2003·Granted Mar 8, 2005·83 cites·16 claims
- 0694US7564118B2Chip and wafer integration process using vertical connectionsIBM·Filed 2008·Granted Jul 21, 2009·23 cites·18 claims
- 0794US6444560B1Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2000·Granted Sep 3, 2002·65 cites·44 claims
- 0893US7388277B2Chip and wafer integration process using vertical connectionsIBM·Filed 2005·Granted Jun 17, 2008·20 cites·18 claims
- 0991US6640021B2Fabrication of a hybrid integrated circuit device including an optoelectronic chipIBM·Filed 2001·Granted Oct 28, 2003·47 cites·20 claims
- 1091US6110806AProcess for precision alignment of chips for mounting on a substrateIBM·Filed 1999·Granted Aug 29, 2000·124 cites·21 claims
- 1189US7071031B2Three-dimensional integrated CMOS-MEMS device and process for making the sameIBM·Filed 2003·Granted Jul 4, 2006·42 cites·29 claims
- 1288US6737297B2Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2002·Granted May 18, 2004·32 cites·16 claims
- 1388US6429045B1Structure and process for multi-chip chip attach with reduced risk of electrostatic discharge damageIBM·Filed 2001·Granted Aug 6, 2002·74 cites·15 claims
- 1487US6856025B2Chip and wafer integration process using vertical connectionsIBM·Filed 2003·Granted Feb 15, 2005·35 cites·4 claims
- 1585US7821120B2Metal filled through via structure for providing vertical wafer-to-wafer interconnectionIBM·Filed 2008·Granted Oct 26, 2010·11 cites·16 claims
- 1685US7049695B1Method and device for heat dissipation in semiconductor modulesIBM·Filed 2005·Granted May 23, 2006·13 cites·26 claims
- 1785US6066513AProcess for precise multichip integration and product thereofIBM·Filed 1998·Granted May 23, 2000·98 cites·18 claims
- 1884US6835589B2Three-dimensional integrated CMOS-MEMS device and process for making the sameIBM·Filed 2002·Granted Dec 28, 2004·48 cites·23 claims
- 1983US7049697B2Process for making fine pitch connections between devices and structure made by the processIBM·Filed 2003·Granted May 23, 2006·22 cites·4 claims
- 2082US5814885AVery dense integrated circuit packageIBM·Filed 1997·Granted Sep 29, 1998·64 cites·12 claims
- 2180US6087199AMethod for fabricating a very dense chip packageIBM·Filed 1998·Granted Jul 11, 2000·58 cites·23 claims
- 2280US5899703AMethod for chip testingIBM·Filed 1997·Granted May 4, 1999·51 cites·6 claims
- 2380US4137103ASilicon integrated circuit region containing implanted arsenic and germaniumIBM·Filed 1978·Granted Jan 30, 1979·32 cites·3 claims
- 2480US4111719AMinimization of misfit dislocations in silicon by double implantation of arsenic and germaniumIBM·Filed 1976·Granted Sep 5, 1978·32 cites·3 claims
- 2579US5081439AThin film resistor and method for producing sameIBM·Filed 1990·Granted Jan 14, 1992·33 cites·17 claims
- 2676US5770884AVery dense integrated circuit packageIBM·Filed 1995·Granted Jun 23, 1998·33 cites·14 claims
- 2774US5998868AVery dense chip packageIBM·Filed 1998·Granted Dec 7, 1999·45 cites·19 claims
- 2870US5866443AVery dense integrated circuit package and method for forming the sameIBM·Filed 1997·Granted Feb 2, 1999·26 cites·8 claims
- 2969US6460265B2Double-sided wafer exposure method and deviceIBM·Filed 1998·Granted Oct 8, 2002·27 cites·10 claims
- 3068US5681775ASoi fabrication processIBM·Filed 1995·Granted Oct 28, 1997·36 cites·32 claims
- 3165US6025638AStructure for precision multichip assemblyIBM·Filed 1998·Granted Feb 15, 2000·35 cites·7 claims
- 3260US3961353AHigh power semiconductor deviceIBM·Filed 1974·Granted Jun 1, 1976·11 cites·6 claims
- 3357US6548325B2Wafer thickness compensation for interchip planarityIBM·Filed 2001·Granted Apr 15, 2003·6 cites·10 claims
- 3453US6333553B1Wafer thickness compensation for interchip planarityIBM·Filed 1999·Granted Dec 25, 2001·16 cites·10 claims
- 3552US2007252287A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2007·Application pending·0 cites
- 3651US2006278998A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2006·Application pending·0 cites
- 3743US2005056943A1Integrated electronic chip and interconnect device and process for making the sameIBM·Filed 2004·Application pending·0 cites
- 3842US6730529B1Method for chip testingIBM·Filed 1999·Granted May 4, 2004·8 cites·6 claims
- 3941US8367543B2Structure and method to improve current-carrying capabilities of C4 jointsIBM·Filed 2006·Granted Feb 5, 2013·0 cites·9 claims
- 4035US4006045AMethod for producing high power semiconductor device using anodic treatment and enhanced diffusionIBM·Filed 1976·Granted Feb 1, 1977·6 cites·7 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →