Inventor · disambiguated record
James S. Koford
Also filed as: KOFORD JAMES · KOFORD JAMES S
81 granted patents·2 pending applications·6,767 citations·filing 1978–2008
99Inventor score
Top patents by PatentIndex Score
83 records- 0199US6557145B2Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 2001·Granted Apr 29, 2003·287 cites·24 claims
- 0298US5777360AHexagonal field programmable gate array architectureLSI LOGIC CORP·Filed 1995·Granted Jul 7, 1998·338 cites·49 claims
- 0397US6026223AAdvanced modular cell placement system with overlap remover with minimal noiseFiled 1996·Granted Feb 15, 2000·269 cites·20 claims
- 0497US5838163ATesting and exercising individual, unsingulated dies on a waferLSI LOGIC CORP·Filed 1995·Granted Nov 17, 1998·137 cites·7 claims
- 0597US5822214ACAD for hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Oct 13, 1998·297 cites·5 claims
- 0697US5495419AIntegrated circuit physical design automation system utilizing optimization process decomposition and parallel processingLSI LOGIC CORP·Filed 1994·Granted Feb 27, 1996·199 cites·17 claims
- 0797US5442282ATesting and exercising individual, unsingulated dies on a waferLSI LOGIC CORP·Filed 1992·Granted Aug 15, 1995·150 cites·3 claims
- 0896US6407434B1Hexagonal architectureLSI LOGIC CORP·Filed 1995·Granted Jun 18, 2002·245 cites·4 claims
- 0996US5650653AMicroelectronic integrated circuit including triangular CMOS "nand" gate deviceLSI LOGIC CORP·Filed 1995·Granted Jul 22, 1997·175 cites·47 claims
- 1096US5636125AComputer implemented method for producing optimized cell placement for integrated circiut chipLSI LOGIC CORP·Filed 1995·Granted Jun 3, 1997·196 cites·17 claims
- 1195US5539325ATesting and exercising individual, unsingulated dies on a waferLSI LOGIC CORP·Filed 1995·Granted Jul 23, 1996·100 cites·20 claims
- 1294US5811863ATransistors having dynamically adjustable characteristicsLSI LOGIC CORP·Filed 1995·Granted Sep 22, 1998·202 cites·47 claims
- 1393US5980093AIntegrated circuit layout routing using multiprocessingLSI LOGIC CORP·Filed 1996·Granted Nov 9, 1999·243 cites·51 claims
- 1493US5973376AArchitecture having diamond shaped or parallelogram shaped cellsLSI LOGIC CORP·Filed 1995·Granted Oct 26, 1999·157 cites·9 claims
- 1593US5742086AHexagonal DRAM arrayLSI LOGIC CORP·Filed 1995·Granted Apr 21, 1998·162 cites·40 claims
- 1693US5389556AIndividually powering-up unsingulated dies on a waferLSI LOGIC CORP·Filed 1992·Granted Feb 14, 1995·148 cites·7 claims
- 1792US6155725ACell placement representation and transposition for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Dec 5, 2000·174 cites·24 claims
- 1892US5914887ACongestion based cost factor computing apparatus for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Jun 22, 1999·176 cites·27 claims
- 1991US6292929B2Advanced modular cell placement systemLSI LOGIC CORP·Filed 1999·Granted Sep 18, 2001·142 cites·22 claims
- 2091US6286128B1Method for design optimization using logical and physical informationMONTEREY DESIGN SYSTEMS INC·Filed 1998·Granted Sep 4, 2001·202 cites·10 claims
- 2191US5889329ATri-directional interconnect architecture for SRAMLSI LOGIC CORP·Filed 1995·Granted Mar 30, 1999·135 cites·65 claims
- 2291US5648661AIntegrated circuit wafer comprising unsingulated dies, and decoder arrangement for individually testing the diesLSI LOGIC CORP·Filed 1994·Granted Jul 15, 1997·134 cites·10 claims
- 2391US5578840AMicroelectronic integrated circuit structure and method using three directional interconnect routing based on hexagonal geometryLIS LOGIC CORP·Filed 1994·Granted Nov 26, 1996·188 cites·9 claims
- 2490US6088519AMethod and system for improving a placement of cells using energetic placement with alternating contraction and expansion operationsLSI LOGIC CORP·Filed 1998·Granted Jul 11, 2000·122 cites·18 claims
- 2590US6067409AAdvanced modular cell placement systemLSI LOGIC CORP·Filed 1997·Granted May 23, 2000·153 cites·23 claims
- 2689US5557533ACell placement alteration apparatus for integrated circuit chip physical design automation systemLSI LOGIC CORP·Filed 1994·Granted Sep 17, 1996·118 cites·37 claims
- 2788US5872380AHexagonal sense cell architectureLSI LOGIC CORP·Filed 1995·Granted Feb 16, 1999·106 cites·27 claims
- 2885US6493658B1Optimization processing for integrated circuit physical design automation system using optimally switched fitness improvement algorithmsLSI LOGIC CORP·Filed 1994·Granted Dec 10, 2002·104 cites·33 claims
- 2984US5568636AMethod and system for improving a placement of cells using energetic placement with alternating contraction and expansion operationsLSI LOGIC CORP·Filed 1994·Granted Oct 22, 1996·78 cites·31 claims
- 3083US5903461AMethod of cell placement for an integrated circuit chip comprising chaotic placement and moving windowsLSI LOGIC CORP·Filed 1997·Granted May 11, 1999·68 cites·40 claims
- 3183US5745363AOptimization processing for integrated circuit physical design automation system using optimally switched cost function computationsLSI LOGIC CORP·Filed 1996·Granted Apr 28, 1998·70 cites·23 claims
- 3283US4377862AMethod of error control in asynchronous communicationsBOEING CO·Filed 1978·Granted Mar 22, 1983·57 cites·26 claims
- 3381US6223332B1Advanced modular cell placement system with overlap remover with minimal noiseLSI LOGIC CORP·Filed 2000·Granted Apr 24, 2001·28 cites·21 claims
- 3481US5742510ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Apr 21, 1998·61 cites·28 claims
- 3580US6134702APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1997·Granted Oct 17, 2000·90 cites·22 claims
- 3680US5875117ASimultaneous placement and routing (SPAR) method for integrated circuit physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Feb 23, 1999·91 cites·32 claims
- 3779US5682322AOptimization processing for integrated circuit physical design automation system using chaotic fitness improvement methodLSI LOGIC CORP·Filed 1994·Granted Oct 28, 1997·76 cites·34 claims
- 3878US5789770AHexagonal architecture with triangular shaped cellsLSI LOGIC CORP·Filed 1995·Granted Aug 4, 1998·53 cites·41 claims
- 3977US6999910B2Method and apparatus for implementing a metamethodologyLSI LOGIC CORP·Filed 2001·Granted Feb 14, 2006·24 cites·7 claims
- 4077US5808330APolydirectional non-orthoginal three layer interconnect architectureLSI LOGIC CORP·Filed 1995·Granted Sep 15, 1998·54 cites·12 claims
- 4176US7076746B2Method and apparatus for mapping platform-based design to multiple foundry processesLSI LOGIC CORP·Filed 2004·Granted Jul 11, 2006·21 cites·31 claims
- 4273US5661663APhysical design automation system and method using hierarchical clusterization and placement improvement based on complete re-placement of cell clustersLSI LOGIC CORP·Filed 1995·Granted Aug 26, 1997·66 cites·41 claims
- 4372US5699265APhysical design automation system and process for designing integrated circuit chips using multiway partitioning with constraintsLSI LOGIC CORP·Filed 1995·Granted Dec 16, 1997·63 cites·22 claims
- 4471US5712793APhysical design automation system and process for designing integrated circuit chips using fuzzy cell clusterizationLSI LOGIC CORP·Filed 1995·Granted Jan 27, 1998·64 cites·36 claims
- 4569US5963975ASingle chip integrated circuit distributed shared memory (DSM) and communications nodesLSI LOGIC CORP·Filed 1997·Granted Oct 5, 1999·55 cites·26 claims
- 4668US5870313AOptimization processing for integrated circuit physical design automation system using parallel moving windowsLSI LOGIC CORP·Filed 1997·Granted Feb 9, 1999·49 cites·49 claims
- 4768US5781439AMethod for producing integrated circuit chip having optimized cell placementLSI LOGIC CORP·Filed 1995·Granted Jul 14, 1998·33 cites·17 claims
- 4867US5815403AFail-safe distributive processing method for producing a highest fitness cell placement for an integrated circuit chipLSI LOGIC CORP·Filed 1994·Granted Sep 29, 1998·45 cites·8 claims
- 4967US5793644ACell placement alteration apparatus for integrated circuit chip physical design automation systemLSI LOGIC CORP·Filed 1996·Granted Aug 11, 1998·44 cites·32 claims
- 5066US6085032AAdvanced modular cell placement system with sinusoidal optimizationLSI LOGIC CORP·Filed 1996·Granted Jul 4, 2000·48 cites·19 claims
Showing the top 50 of 83 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →