Inventor · disambiguated record
Sridhar Govindaraju
Also filed as: GOVINDARAJU SRIDHAR · GOVINDARAJU SRIDHAR S
18 granted patents·6 pending applications·31 citations·filing 2005–2024
91Inventor score
Top patents by PatentIndex Score
24 records- 0192US10847423B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2019·Granted Nov 24, 2020·4 cites·25 claims
- 0289US2024413016A1Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2024·Application pending·0 cites
- 0386US12094780B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2023·Granted Sep 17, 2024·0 cites·20 claims
- 0484US10468305B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2017·Granted Nov 5, 2019·2 cites·25 claims
- 0584US9704798B2Using materials with different etch rates to fill trenches in semiconductor devicesINTEL CORP·Filed 2013·Granted Jul 11, 2017·10 cites·25 claims
- 0681US11756833B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·23 claims
- 0778US11217582B2Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal wallsINTEL CORP·Filed 2018·Granted Jan 4, 2022·2 cites·13 claims
- 0876US7758238B2Temperature measurement with reduced extraneous infrared in a processing chamberINTEL CORP·Filed 2008·Granted Jul 20, 2010·8 cites·15 claims
- 0974US11380592B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2020·Granted Jul 5, 2022·0 cites·25 claims
- 1072US7892971B2Sub-second annealing processes for semiconductor devicesINTEL CORP·Filed 2008·Granted Feb 22, 2011·5 cites·15 claims
- 1165US11688792B2Dual self-aligned gate endcap (SAGE) architecturesINTEL CORP·Filed 2021·Granted Jun 27, 2023·0 cites·25 claims
- 1264US11605632B2Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal wallsINTEL CORP·Filed 2021·Granted Mar 14, 2023·0 cites·20 claims
- 1360US9761497B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2016·Granted Sep 12, 2017·0 cites·9 claims
- 1460US9281401B2Techniques and configurations to reduce transistor gate short defectsINTEL CORP·Filed 2013·Granted Mar 8, 2016·0 cites·8 claims
- 1557US2025107209A1Material layer containing molybdenum to protect gate dielectricINTEL CORP·Filed 2023·Application pending·0 cites
- 1654US11205708B2Dual self-aligned gate endcap (SAGE) architecturesINTEL CORP·Filed 2018·Granted Dec 21, 2021·0 cites·21 claims
- 1748US11705453B2Self-aligned gate endcap (SAGE) architecture having local interconnectsINTEL CORP·Filed 2019·Granted Jul 18, 2023·0 cites·21 claims
- 1843US11329138B2Self-aligned gate endcap (SAGE) architecture having endcap plugsINTEL CORP·Filed 2018·Granted May 10, 2022·0 cites·20 claims
- 1942US7790587B2Method to reduce junction leakage through partial regrowth with ultrafast anneal and structures formed therebyINTEL CORP·Filed 2006·Granted Sep 7, 2010·0 cites·8 claims
- 2042US2008242117A1Apparatus to reduce wafer edge temperature and breakage of wafersRAMANARAYANAN PANCHAPAKESAN·Filed 2007·Application pending·0 cites
- 2139US2015179469A1Method and system to control polish rate variation introduced by device density differencesGOVINDARAJU SRIDHAR·Filed 2013·Application pending·0 cites
- 2238US2014011373A1Annealing a sacrificial layerKILLAMPALLI ARAVIND·Filed 2011·Application pending·0 cites
- 2332US2007099404A1Implant and anneal amorphization processGOVINDARAJU SRIDHAR·Filed 2005·Application pending·0 cites
- 2431US11978776B2Non-planar semiconductor device having conforming ohmic contactsINTEL CORP·Filed 2016·Granted May 7, 2024·0 cites·9 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →