Inventor · disambiguated record
Todd Deschepper
Also filed as: DESCHEPPER TODD · DESCHEPPER TODD J
16 granted patents·1,201 citations·filing 1995–1998
96Inventor score
Technology areasG06F
Files withCOMPAQ COMPUTER CORP16
Top patents by PatentIndex Score
16 records- 0192US6212590B1Computer system having integrated bus bridge design with delayed transaction arbitration mechanism employed within laptop computer docked to expansion baseCOMPAQ COMPUTER CORP·Filed 1998·Granted Apr 3, 2001·198 cites·13 claims
- 0287US6199131B1Computer system employing optimized delayed transaction arbitration techniqueCOMPAQ COMPUTER CORP·Filed 1997·Granted Mar 6, 2001·141 cites·29 claims
- 0386US5987555ADynamic delayed transaction discard counter in a bus bridge of a computer systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Nov 16, 1999·126 cites·27 claims
- 0485US5721935AApparatus and method for entering low power mode in a computer systemCOMPAQ COMPUTER CORP·Filed 1997·Granted Feb 24, 1998·122 cites·29 claims
- 0577US6357013B1Circuit for setting computer system bus signals to predetermined states in low power modeCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 12, 2002·71 cites·25 claims
- 0676US6226700B1Computer system with bridge logic that includes an internal modular expansion bus and a common master interface for internal master devicesCOMPAQ COMPUTER CORP·Filed 1998·Granted May 1, 2001·81 cites·36 claims
- 0773US6065122ASmart battery power management in a computer systemCOMPAQ COMPUTER CORP·Filed 1998·Granted May 16, 2000·74 cites·31 claims
- 0872US5991833AComputer system with bridge logic that reduces interference to CPU cycles during secondary bus transactionsCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 23, 1999·66 cites·25 claims
- 0970US6145029AComputer system with enhanced docking supportCOMPAQ COMPUTER CORP·Filed 1998·Granted Nov 7, 2000·55 cites·20 claims
- 1070US6070215AComputer system with improved transition to low power operationCOMPAQ COMPUTER CORP·Filed 1998·Granted May 30, 2000·54 cites·27 claims
- 1169US6199134B1Computer system with bridge logic that asserts a system management interrupt signal when an address is made to a trapped address and which also completes the cycle to the target addressCOMPAQ COMPUTER CORP·Filed 1998·Granted Mar 6, 2001·58 cites·32 claims
- 1267US6094700ASerial bus system for sending multiple frames of unique dataCOMPAQ COMPUTER CORP·Filed 1998·Granted Jul 25, 2000·52 cites·30 claims
- 1357US6101566AComputer system with bridge logic that includes an internal modular expansion bus and a common target interface for internal target devicesCOMPAQ COMPUTER CORP·Filed 1998·Granted Aug 8, 2000·34 cites·37 claims
- 1457US5740454ACircuit for setting computer system bus signals to predetermined states in low power modeCOMPAQ COMPUTER CORP·Filed 1995·Granted Apr 14, 1998·29 cites·52 claims
- 1555US5796992ACircuit for switching between synchronous and asynchronous memory refresh cycles in low power modeCOMPAQ COMPUTER CORP·Filed 1995·Granted Aug 18, 1998·30 cites·35 claims
- 1638US6230227B1Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridgeCOMPAQ COMPUTER CORP·Filed 1998·Granted May 8, 2001·10 cites·24 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →