Inventor · disambiguated record
Markus Kaltenbach
Also filed as: KALTENBACH MARKUS
66 granted patents·4 pending applications·167 citations·filing 1999–2022
98Inventor score
Top patents by PatentIndex Score
70 records- 0197US9720696B2Independent mapping of threadsIBM·Filed 2014·Granted Aug 1, 2017·30 cites·6 claims
- 0293US9870229B2Independent mapping of threadsIBM·Filed 2015·Granted Jan 16, 2018·8 cites·9 claims
- 0393US9760375B2Register files for storing data operated on by instructions of multiple widthsIBM·Filed 2014·Granted Sep 12, 2017·23 cites·12 claims
- 0493US9740486B2Register files for storing data operated on by instructions of multiple widthsIBM·Filed 2014·Granted Aug 22, 2017·23 cites·13 claims
- 0592US10380033B2Multi-engine address translation facilityIBM·Filed 2017·Granted Aug 13, 2019·6 cites·8 claims
- 0692US9207995B2Mechanism to speed-up multithreaded execution by register file write port reallocationBOERSMA MAARTEN J·Filed 2011·Granted Dec 8, 2015·26 cites·12 claims
- 0789US10083124B1Translating virtual memory addresses to physical addressesIBM·Filed 2017·Granted Sep 25, 2018·6 cites·20 claims
- 0884US7707562B1Code translation verificationKALTENBACH MARKUS·Filed 2005·Granted Apr 27, 2010·19 cites·26 claims
- 0981US10423412B2Instructions to count contiguous register elements having a specific value in a selected locationIBM·Filed 2015·Granted Sep 24, 2019·2 cites·11 claims
- 1080US10387150B2Instructions to count contiguous register elements having a specific value in a selected locationIBM·Filed 2015·Granted Aug 20, 2019·2 cites·20 claims
- 1176US10585797B2Operating different processor cache levelsIBM·Filed 2017·Granted Mar 10, 2020·1 cites·4 claims
- 1276US8949575B2Reversing processing order in half-pumped SIMD execution units to achieve K cycle issue-to-issue latencyBOERSMA MAARTEN J·Filed 2011·Granted Feb 3, 2015·4 cites·10 claims
- 1375US10380032B2Multi-engine address translation facilityIBM·Filed 2017·Granted Aug 13, 2019·1 cites·14 claims
- 1474US8903882B2Method and data processing unit for calculating at least one multiply-sum of two carry-less multiplications of two input operands, data processing program and computer program productBOERSMA MAARTEN J·Filed 2011·Granted Dec 2, 2014·4 cites·13 claims
- 1572US10169234B2Translation lookaside buffer purging with concurrent cache updatesIBM·Filed 2017·Granted Jan 1, 2019·1 cites·10 claims
- 1671US9164725B2Apparatus and method for calculating an SHA-2 hash function in a general purpose processorBOERSMA MAARTEN J·Filed 2011·Granted Oct 20, 2015·3 cites·20 claims
- 1768US10956341B2Multi-engine address translation facilityIBM·Filed 2020·Granted Mar 23, 2021·0 cites·18 claims
- 1868US8782788B2Systems, methods, and apparatus for improved application securityLONOCLOUD INC·Filed 2012·Granted Jul 15, 2014·4 cites·25 claims
- 1967US11182293B2Operating different processor cache levelsIBM·Filed 2019·Granted Nov 23, 2021·0 cites·19 claims
- 2067US11169922B2Method and arrangement for saving cache powerIBM·Filed 2019·Granted Nov 9, 2021·0 cites·6 claims
- 2167US11144323B2Independent mapping of threadsIBM·Filed 2019·Granted Oct 12, 2021·0 cites·18 claims
- 2267US9506986B2Integrated circuit chip and a method for testing the sameIBM·Filed 2014·Granted Nov 29, 2016·1 cites·16 claims
- 2366US11972259B2Instructions to count a number of contiguous register elements having specific values in a selected locationIBM·Filed 2019·Granted Apr 30, 2024·0 cites·17 claims
- 2466US11972260B2Instructions to count a number of contiguous register elements having specific values in a selected locationIBM·Filed 2019·Granted Apr 30, 2024·0 cites·9 claims
- 2566US10997079B2Method and arrangement for saving cache powerIBM·Filed 2019·Granted May 4, 2021·0 cites·14 claims
- 2666US10635603B2Multi-engine address translation facilityIBM·Filed 2019·Granted Apr 28, 2020·0 cites·7 claims
- 2766US10621105B2Multi-engine address translation facilityIBM·Filed 2019·Granted Apr 14, 2020·0 cites·14 claims
- 2865US10970214B2Selective downstream cache processing for data accessIBM·Filed 2019·Granted Apr 6, 2021·0 cites·17 claims
- 2965US10956328B2Selective downstream cache processing for data accessIBM·Filed 2019·Granted Mar 23, 2021·0 cites·19 claims
- 3065US10740240B2Method and arrangement for saving cache powerIBM·Filed 2019·Granted Aug 11, 2020·0 cites·1 claims
- 3164US11372776B2Method and apparatus for an efficient TLB lookupIBM·Filed 2019·Granted Jun 28, 2022·0 cites·20 claims
- 3264US10317465B2Integrated circuit chip and a method for testing the sameIBM·Filed 2018·Granted Jun 11, 2019·0 cites·4 claims
- 3364US2019213129A1Selective downstream cache processing for data accessIBM·Filed 2019·Application pending·0 cites
- 3462US7844422B2Method and system for changing a description for a state transition function of a state machine engineIBM·Filed 2007·Granted Nov 30, 2010·2 cites·7 claims
- 3561US10572384B2Operating different processor cache levelsIBM·Filed 2017·Granted Feb 25, 2020·0 cites·11 claims
- 3661US10545762B2Independent mapping of threadsIBM·Filed 2017·Granted Jan 28, 2020·0 cites·20 claims
- 3761US10528472B2Method and arrangement for saving cache powerIBM·Filed 2017·Granted Jan 7, 2020·0 cites·14 claims
- 3861US10409724B2Selective downstream cache processing for data accessIBM·Filed 2017·Granted Sep 10, 2019·0 cites·4 claims
- 3961US10268582B2Operating different processor cache levelsIBM·Filed 2018·Granted Apr 23, 2019·0 cites·1 claims
- 4060US10417127B2Selective downstream cache processing for data accessIBM·Filed 2017·Granted Sep 17, 2019·0 cites·12 claims
- 4160US10229061B2Method and arrangement for saving cache powerIBM·Filed 2017·Granted Mar 12, 2019·0 cites·3 claims
- 4260US10006965B2Integrated circuit chip and a method for testing the sameIBM·Filed 2016·Granted Jun 26, 2018·0 cites·17 claims
- 4359US11977486B2Shadow pointer directory in an inclusive hierarchical cacheIBM·Filed 2022·Granted May 7, 2024·0 cites·20 claims
- 4459US11748266B1Special tracking pool enhancement for core local cache address invalidatesIBM·Filed 2022·Granted Sep 5, 2023·0 cites·20 claims
- 4558US10540293B2Method and apparatus for an efficient TLB lookupIBM·Filed 2017·Granted Jan 21, 2020·0 cites·12 claims
- 4658US7703058B2Method and system for changing a description for a state transition function of a state machine engineIBM·Filed 2007·Granted Apr 20, 2010·1 cites·11 claims
- 4756US10649912B2Method and apparatus for an efficient TLB lookupIBM·Filed 2017·Granted May 12, 2020·0 cites·13 claims
- 4856US10592414B2Filtering of redundantly scheduled write passesIBM·Filed 2017·Granted Mar 17, 2020·0 cites·18 claims
- 4956US9361267B2Splitable and scalable normalizer for vector dataBOERSMA MAARTEN J·Filed 2013·Granted Jun 7, 2016·0 cites·4 claims
- 5056US9361268B2Splitable and scalable normalizer for vector dataIBM·Filed 2014·Granted Jun 7, 2016·0 cites·5 claims
Showing the top 50 of 70 patent records by PatentIndex Score.
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