Inventor · disambiguated record
Robert Hathaway
Also filed as: HATHAWAY ROBERT · HATHAWAY ROBERT G
16 granted patents·3 pending applications·224 citations·filing 1998–2021
93Inventor score
Top patents by PatentIndex Score
19 records- 0196US7398449B1Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory moduleAZUL SYSTEMS INC·Filed 2005·Granted Jul 8, 2008·49 cites·12 claims
- 0293US8051227B1Programmable queue structures for multiprocessorsERICSSON TELEFON AB L M·Filed 2010·Granted Nov 1, 2011·32 cites·19 claims
- 0392US7366847B2Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tagAZUL SYSTEMS INC·Filed 2006·Granted Apr 29, 2008·31 cites·20 claims
- 0488US8099651B2Subsystem and method for encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use in a 76-bit memory moduleNORMOYLE KEVIN B·Filed 2008·Granted Jan 17, 2012·23 cites·6 claims
- 0585US10747457B2Technologies for processing network packets in agent-mesh architecturesINTEL CORP·Filed 2017·Granted Aug 18, 2020·2 cites·25 claims
- 0683US7225300B1Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor systemAZUL SYSTEMS INC·Filed 2004·Granted May 29, 2007·36 cites·20 claims
- 0781US8656139B2Digital processor for processing long and short pointers and converting each between a common formatMEIER STEPHAN·Filed 2011·Granted Feb 18, 2014·8 cites·27 claims
- 0878US8914581B2Method and apparatus for accessing cache memoryHATHAWAY ROBERT·Filed 2010·Granted Dec 16, 2014·9 cites·12 claims
- 0972US8402248B2Explicitly regioned memory organization in a network elementMEIER STEPHAN·Filed 2010·Granted Mar 19, 2013·4 cites·19 claims
- 1068US12160369B2Processor related communicationsINTEL CORP·Filed 2019·Granted Dec 3, 2024·1 cites·20 claims
- 1166US9311148B2Pseudo-random hardware resource allocation through the plurality of resource controller based on non-repeating sequence of index list entriesERICSSON TELEFON AB L M·Filed 2012·Granted Apr 12, 2016·2 cites·19 claims
- 1259US9419911B2Method and system for packet job scheduler in data processing based on workload self-learningERICSSON TELEFON AB L M·Filed 2012·Granted Aug 16, 2016·1 cites·21 claims
- 1344US9317289B2Acknowledgement forwardingERICSSON TELEFON AB L M·Filed 2012·Granted Apr 19, 2016·0 cites·16 claims
- 1443US2014181474A1Atomic write and read microprocessor instructionsERICSSON TELEFON AB L M·Filed 2012·Application pending·0 cites
- 1543US2021288910A1Network interface device with support for hierarchical quality of service (qos)INTEL CORP·Filed 2021·Application pending·0 cites
- 1642US6105128AMethod and apparatus for dispatching instructions to execution units in wavesINTEL CORP·Filed 1998·Granted Aug 15, 2000·14 cites·26 claims
- 1740US5978898AAllocating registers in a superscalar machineINTEL CORP·Filed 1998·Granted Nov 2, 1999·12 cites·38 claims
- 1839US2011276784A1Hierarchical multithreaded processingERICSSON TELEFON AB L M·Filed 2010·Application pending·0 cites
- 1926US8700874B2Digital counter segmented into short and long access time memoryCHEN EDMUND G·Filed 2010·Granted Apr 15, 2014·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →