Inventor · disambiguated record
David B. Papworth
Also filed as: PAPWORTH DAVID · PAPWORTH DAVID B
60 granted patents·4,313 citations·filing 1984–2022
99Inventor score
Top patents by PatentIndex Score
60 records- 0196US5721855AMethod for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder bufferINTEL CORP·Filed 1996·Granted Feb 24, 1998·335 cites·23 claims
- 0295US5604877AMethod and apparatus for resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1994·Granted Feb 18, 1997·209 cites·28 claims
- 0394US4833599AHierarchical priority branch handling for parallel execution in a parallel processorMULTIFLOW COMPUTER INC·Filed 1987·Granted May 23, 1989·233 cites·9 claims
- 0494US4777594AData processing apparatus and method employing instruction flow predictionPRIME COMPUTER INC·Filed 1984·Granted Oct 11, 1988·116 cites·21 claims
- 0592US10282296B2Zeroing a cache lineINTEL CORP·Filed 2016·Granted May 7, 2019·7 cites·22 claims
- 0691US5574871AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1994·Granted Nov 12, 1996·122 cites·17 claims
- 0790US5179680AInstruction storage and cache miss recovery in a high speed multiprocessing parallel processing apparatusDIGITAL EQUIPMENT CORP·Filed 1991·Granted Jan 12, 1993·155 cites·3 claims
- 0889US5555432ACircuit and method for scheduling instructions by predicting future availability of resources required for executionINTEL CORP·Filed 1994·Granted Sep 10, 1996·108 cites·7 claims
- 0989US4920477AVirtual address table look aside buffer miss recovery method and apparatusMULTIFLOW COMPUTER INC·Filed 1987·Granted Apr 24, 1990·120 cites·6 claims
- 1088US5778245AMethod and apparatus for dynamic allocation of multiple buffers in a processorINTEL CORP·Filed 1994·Granted Jul 7, 1998·131 cites·22 claims
- 1188US5751983AOut-of-order processor with a memory subsystem which handles speculatively dispatched load operationsFiled 1995·Granted May 12, 1998·140 cites·26 claims
- 1288US5057837AInstruction storage method with a compressed format using a mask wordDIGITAL EQUIPMENT CORP·Filed 1990·Granted Oct 15, 1991·139 cites·9 claims
- 1388US4760519AData processing apparatus and method employing collision detection and predictionPRIME COMPUTER INC·Filed 1986·Granted Jul 26, 1988·86 cites·16 claims
- 1485US5627985ASpeculative and committed resource files in an out-of-order processorINTEL CORP·Filed 1994·Granted May 6, 1997·112 cites·33 claims
- 1584US5812839ADual prediction branch system having two step of branch recovery process which activated only when mispredicted branch is the oldest instruction in the out-of-order unitINTEL CORP·Filed 1997·Granted Sep 22, 1998·118 cites·32 claims
- 1683US5586278AMethod and apparatus for state recovery following branch misprediction in an out-of-order microprocessorINTEL CORP·Filed 1996·Granted Dec 17, 1996·109 cites·18 claims
- 1783US5404473AApparatus and method for handling string operations in a pipelined processorINTEL CORP·Filed 1994·Granted Apr 4, 1995·109 cites·37 claims
- 1882US11294809B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2018·Granted Apr 5, 2022·2 cites·7 claims
- 1981US6079014AProcessor that redirects an instruction fetch pipeline immediately upon detection of a mispredicted branch while committing prior instructions to an architectural stateINTEL CORP·Filed 1997·Granted Jun 20, 2000·101 cites·23 claims
- 2081US5584038AEntry allocation in a circular buffer using wrap bits indicating whether a queue of the circular buffer has been traversedINTEL CORP·Filed 1996·Granted Dec 10, 1996·89 cites·8 claims
- 2181US4561051AMemory access method and apparatus in multiple processor systemsPRIME COMPUTER INC·Filed 1984·Granted Dec 24, 1985·56 cites·12 claims
- 2280US6349380B1Linear address extension and mapping to physical memory using 4 and 8 byte page table entries in a 32-bit microprocessorINTEL CORP·Filed 1999·Granted Feb 19, 2002·91 cites·18 claims
- 2380US5604753AMethod and apparatus for performing error correction on data from an external memoryINTEL CORP·Filed 1994·Granted Feb 18, 1997·97 cites·29 claims
- 2479US5768576AMethod and apparatus for predicting and handling resolving return from subroutine instructions in a computer processorINTEL CORP·Filed 1996·Granted Jun 16, 1998·75 cites·19 claims
- 2579US5606670AMethod and apparatus for signalling a store buffer to output buffered store data for a load operation on an out-of-order execution computer systemINTEL CORP·Filed 1996·Granted Feb 25, 1997·80 cites·32 claims
- 2678US5687338AMethod and apparatus for maintaining a macro instruction for refetching in a pipelined processorINTEL CORP·Filed 1995·Granted Nov 11, 1997·81 cites·6 claims
- 2776US10469557B2QoS based binary translation and application streamingINTEL CORP·Filed 2016·Granted Nov 5, 2019·2 cites·14 claims
- 2876US5809271AMethod and apparatus for changing flow of control in a processorINTEL CORP·Filed 1995·Granted Sep 15, 1998·63 cites·7 claims
- 2976US5729728AMethod and apparatus for predicting, clearing and redirecting unpredicted changes in instruction flow in a microprocessorINTEL CORP·Filed 1996·Granted Mar 17, 1998·67 cites·49 claims
- 3076US5561814AMethods and apparatus for determining memory operating characteristics for given memory locations via assigned address rangesINTEL CORP·Filed 1993·Granted Oct 1, 1996·59 cites·38 claims
- 3175US5471633AIdiom recognizer within a register alias tableINTEL CORP·Filed 1994·Granted Nov 28, 1995·67 cites·56 claims
- 3275US5452426ACoordinating speculative and committed state register source data and immediate source data in a processorINTEL CORP·Filed 1994·Granted Sep 19, 1995·66 cites·44 claims
- 3373US12130740B2Apparatuses and methods for a processor architectureINTEL CORP·Filed 2022·Granted Oct 29, 2024·0 cites·15 claims
- 3471US5809325ACircuit and method for scheduling instructions by predicting future availability of resources required for executionINTEL CORP·Filed 1996·Granted Sep 15, 1998·44 cites·8 claims
- 3570US5974523AMechanism for efficiently overlapping multiple operand types in a microprocessorINTEL CORP·Filed 1996·Granted Oct 26, 1999·40 cites·27 claims
- 3670US5546597AReady selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction executionINTEL CORP·Filed 1994·Granted Aug 13, 1996·51 cites·22 claims
- 3768US5903751AMethod and apparatus for implementing a branch target buffer in CISC processorINTEL CORP·Filed 1997·Granted May 11, 1999·38 cites·3 claims
- 3868US5564056AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1994·Granted Oct 8, 1996·41 cites·10 claims
- 3968US5564111AMethod and apparatus for implementing a non-blocking translation lookaside bufferINTEL CORP·Filed 1994·Granted Oct 8, 1996·46 cites·18 claims
- 4067US6393550B1Method and apparatus for pipeline streamlining where resources are immediate or certainly retiredINTEL CORP·Filed 1995·Granted May 21, 2002·50 cites·20 claims
- 4165US5826109AMethod and apparatus for performing multiple load operations to the same memory location in a computer systemINTEL CORP·Filed 1996·Granted Oct 20, 1998·49 cites·18 claims
- 4265US5574942AHybrid execution unit for complex microprocessorINTEL CORP·Filed 1996·Granted Nov 12, 1996·54 cites·29 claims
- 4365US5553256AApparatus for pipeline streamlining where resources are immediate or certainly retiredINTEL CORP·Filed 1995·Granted Sep 3, 1996·49 cites·5 claims
- 4465US5307506AHigh bandwidth multiple computer bus apparatusDIGITAL EQUIPMENT CORP·Filed 1992·Granted Apr 26, 1994·51 cites·13 claims
- 4564US9525586B2QoS based binary translation and application streamingINTEL CORP·Filed 2013·Granted Dec 20, 2016·2 cites·13 claims
- 4663US5615385AMethod and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renamingINTEL CORP·Filed 1995·Granted Mar 25, 1997·37 cites·6 claims
- 4762US5778407AMethods and apparatus for determining operating characteristics of a memory element based on its physical locationINTEL CORP·Filed 1996·Granted Jul 7, 1998·35 cites·7 claims
- 4862US5588126AMethods and apparatus for fordwarding buffered store data on an out-of-order execution computer systemINTEL CORP·Filed 1995·Granted Dec 24, 1996·36 cites·8 claims
- 4961US5751986AComputer system with self-consistent ordering mechanismINTEL CORP·Filed 1997·Granted May 12, 1998·39 cites·34 claims
- 5060US5944817AMethod and apparatus for implementing a set-associative branch target bufferINTEL CORP·Filed 1998·Granted Aug 31, 1999·27 cites·4 claims
Showing the top 50 of 60 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →