Inventor · disambiguated record
Ryan Abel Heckendorf
Also filed as: HECKENDORF RYAN A · HECKENDORF RYAN ABEL
13 granted patents·4 pending applications·25 citations·filing 2004–2010
87Inventor score
Top patents by PatentIndex Score
17 records- 0182US7558908B2Structure of sequencers that perform initial and periodic calibrations in a memory systemIBM·Filed 2007·Granted Jul 7, 2009·11 cites·17 claims
- 0267US7380083B2Memory controller capable of locating an open command cycle to issue a precharge packetIBM·Filed 2005·Granted May 27, 2008·4 cites·5 claims
- 0363US7490204B2Using constraints to simplify a memory controllerIBM·Filed 2005·Granted Feb 10, 2009·3 cites·4 claims
- 0462US8792332B2Implementing lane shuffle for fault-tolerant communication linksHECKENDORF RYAN ABEL·Filed 2010·Granted Jul 29, 2014·2 cites·14 claims
- 0560US7752379B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2009·Granted Jul 6, 2010·1 cites·8 claims
- 0652US7487318B2Managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2007·Granted Feb 3, 2009·0 cites·4 claims
- 0749US7305517B2Structure of sequencers that perform initial and periodic calibrations in a memory systemIBM·Filed 2004·Granted Dec 4, 2007·1 cites·17 claims
- 0849US7272699B2Flexible sub-column to sub-row mapping for sub-page activation in XDR™ DRAMsIBM·Filed 2004·Granted Sep 18, 2007·1 cites·14 claims
- 0948US7321950B2Method and apparatus for managing write-to-read turnarounds in an early read after write memory systemIBM·Filed 2005·Granted Jan 22, 2008·0 cites·14 claims
- 1046US7321961B2Method and apparatus to avoid collisions between row activate and column read or column write commandsIBM·Filed 2004·Granted Jan 22, 2008·0 cites·25 claims
- 1140US7613873B2Deferring refreshes during calibrations in memory systemsIBM·Filed 2008·Granted Nov 3, 2009·0 cites·8 claims
- 1240US7356642B2Deferring refreshes during calibrations in memory systemsIBM·Filed 2004·Granted Apr 8, 2008·2 cites·4 claims
- 1340US2008183916A1Using Extreme Data Rate Memory Commands to Scrub and Refresh Double Data Rate MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 1440US2008168206A1Methods and Apparatus for Interfacing a Processor and a MemoryBELLOWS MARK DAVID·Filed 2007·Application pending·0 cites
- 1539US2008229007A1Enhancements to an XDR Memory Controller to Allow for Conversion to DDR2BELLOWS MARK D·Filed 2007·Application pending·0 cites
- 1638US8493842B2Implementing exchange of failing lane information for fault-tolerant communication linksHECKENDORF RYAN ABEL·Filed 2010·Granted Jul 23, 2013·0 cites·17 claims
- 1728US2007121398A1Memory controller capable of handling precharge-to-precharge restrictionsBELLOWS MARK D·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →