Inventor · disambiguated record
Anadi Srivastava
Also filed as: SRIVASTAVA ANADI
3 granted patents·6 pending applications·8 citations·filing 2006–2023
59Inventor score
Top patents by PatentIndex Score
9 records- 0167US7563700B2Method for improving self-aligned silicide extendibility with spacer recess using an aggregated spacer recess etch (ASRE) integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Jul 21, 2009·6 cites·21 claims
- 0253US7820539B2Method for separately optimizing spacer width for two transistor groups using a recess spacer etch (RSE) integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Oct 26, 2010·2 cites·24 claims
- 0352US2025167192A1Integrated circuit die stack with a bridge dieADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 0451US2025098184A1Hybrid methods and structures for increasing capacitance density in integrated passive devicesADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 0551US2025096161A1Methods and structures for increasing capacitance density in integrated passive devicesADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 0649US2025323212A1Systems and methods for stack construction of a semiconductor device having redistribution layers in a silicon carrierADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 0748US2025293210A1Systems and methods for packaging a semiconductor deviceADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 0836US2007197011A1Method for improving self-aligned silicide extendibility with spacer recess using a stand-alone recess etch integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Application pending·0 cites
- 0923US7902021B2Method for separately optimizing spacer width for two or more transistor classes using a recess spacer integrationFREESCALE SEMICONDUCTOR INC·Filed 2006·Granted Mar 8, 2011·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →