Inventor · disambiguated record
Gernot Steinlesberger
Also filed as: STEINLESBERGER GERNOT
3 granted patents·8 pending applications·28 citations·filing 2004–2008
66Inventor score
Top patents by PatentIndex Score
11 records- 0187US7807563B2Method for manufacturing a layer arrangement and layer arrangementINFINEON TECHNOLOGIES AG·Filed 2007·Granted Oct 5, 2010·23 cites·18 claims
- 0256US6946386B2Process for producing ultrathin homogenous metal layersINFINEON TECHNOLOGIES AG·Filed 2004·Granted Sep 20, 2005·3 cites·8 claims
- 0353US8664657B2Electrical circuit with a nanostructure and method for producing a contact connection of a nanostructureDUESBERG GEORG·Filed 2005·Granted Mar 4, 2014·2 cites·22 claims
- 0442US2005118342A1Process for depositing a catalystFiled 2004·Application pending·0 cites
- 0537US2008197384A1Field Effect Transistor ArrangementHARTWICH JESSICA·Filed 2008·Application pending·0 cites
- 0637US2007018218A1Fin field effect transistor memory cell, fin field effect transistor memory cell arrangement and method for producing the fin field effect transistor memory cellKRETZ JOHANNES·Filed 2006·Application pending·0 cites
- 0737US2007010094A1Method for depositing a conductive carbon material on a semiconductor for forming a Schottky contact and semiconductor contact deviceKREUPL FRANZ·Filed 2006·Application pending·0 cites
- 0833US2009046499A1Integrated circuit including memory having limited readQIMONDA AG·Filed 2008·Application pending·0 cites
- 0932US2008126624A1Memory buffer and method for buffering dataPRETE EDOARDO·Filed 2006·Application pending·0 cites
- 1031US2009268513A1Memory device with different types of phase change memoryDE AMBROGGI LUCA·Filed 2008·Application pending·0 cites
- 1131US2009199043A1Error correction in an integrated circuit with an array of memory cellsSCHROGMEIER PETER·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →