Inventor · disambiguated record
Sasikumar Cherubal
Also filed as: CHERUBAL SASIKUMAR · CHERUBAL SASIKUMAR P
6 granted patents·3 pending applications·92 citations·filing 2001–2019
83Inventor score
Files withGEORGIA TECH RES INST3ANORA LLC1ARDEXT TECHNOLOGIES INC1TEXAS INSTRUMENTS INC1VOORAKARANAM RAM1
Top patents by PatentIndex Score
9 records- 0187US11150292B1Voltage spike detector and system for detecting voltage spikes in semiconductor devicesANORA LLC·Filed 2019·Granted Oct 19, 2021·4 cites·20 claims
- 0282US7006939B2Method and apparatus for low cost signature testing for analog and RF circuitsGEORGIA TECH RES INST·Filed 2001·Granted Feb 28, 2006·36 cites·17 claims
- 0382US6625785B2Method for diagnosing process parameter variations from measurements in analog circuitsGEORGIA TECH RES INST·Filed 2001·Granted Sep 23, 2003·32 cites·8 claims
- 0459US6476741B2Method and system for making optimal estimates of linearity metrics of analog-to-digital convertersGEORGIA TECH RES INST·Filed 2001·Granted Nov 5, 2002·11 cites·17 claims
- 0542US7109902B2Method and system for sampling a signalTEXAS INSTRUMENTS INC·Filed 2004·Granted Sep 19, 2006·3 cites·19 claims
- 0641US6964004B2Method and apparatus for testing a system-on-a-chipARDEXT TECHNOLOGIES INC·Filed 2002·Granted Nov 8, 2005·6 cites·5 claims
- 0740US2002136337A1Method and apparatus for high-resolution jitter measurementFiled 2002·Application pending·0 cites
- 0836US2006106555A1Method for using an alternate performance test to reduce test time and improve manufacturing yieldVOORAKARANAM RAM·Filed 2005·Application pending·0 cites
- 0932US2004148549A1Method for using an alternate performance test to reduce test time and improve manufacturing yieldFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →