Inventor · disambiguated record
George Apostol, Jr.
Also filed as: APOSTOL GEORGE · APOSTOL JR GEORGE
19 granted patents·354 citations·filing 1992–2023
95Inventor score
Technology areasG06F
Files withAVAGO TECH INT SALES PTE LID5XEROX CORP5CAVIUM NETWORKS INC3PMC SIERRA INC3BRECIS COMM CORP1
Top patents by PatentIndex Score
19 records- 0195US11947472B2Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoCAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Apr 2, 2024·3 cites·20 claims
- 0287US6247084B1Integrated circuit with unified memory system and dual bus architectureLSI LOGIC CORP·Filed 1998·Granted Jun 12, 2001·167 cites·19 claims
- 0382US12326813B2Heterogeneous architecture, delivered by cxl based cached switch SOC and extensible via cxloverethernet (COE) protocolsAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Jun 10, 2025·0 cites·20 claims
- 0478US7243179B2On-chip inter-subsystem communicationCAVIUM NETWORKS INC·Filed 2006·Granted Jul 10, 2007·6 cites·14 claims
- 0577US12386751B2Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOC and extensible via cxloverethernet (COE) protocolsAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Aug 12, 2025·0 cites·10 claims
- 0677US11989143B2Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SoCAVAGO TECH INT SALES PTE LID·Filed 2022·Granted May 21, 2024·0 cites·20 claims
- 0776US12259816B2Composable infrastructure enabled by heterogeneous architecture, delivered by CXL based cached switch SOCAVAGO TECH INT SALES PTE LID·Filed 2022·Granted Mar 25, 2025·0 cites·12 claims
- 0870US7349424B2On-chip inter-subsystem communication including concurrent data traffic routingPMC SIERRA INC·Filed 2006·Granted Mar 25, 2008·3 cites·16 claims
- 0970US7095752B2On-chip inter-subsystem communication including concurrent data traffic routingPMC SIERRA INC·Filed 2002·Granted Aug 22, 2006·11 cites·42 claims
- 1061US6677786B2Multi-service processor clocking systemBRECIS COMM CORP·Filed 2002·Granted Jan 13, 2004·16 cites·35 claims
- 1161US5450547ABus interface using pending channel information stored in single circular queue for controlling channels of data transfer within multiple FIFO devicesXEROX CORP·Filed 1992·Granted Sep 12, 1995·41 cites·1 claims
- 1260US7096292B2On-chip inter-subsystem communicationCAVIUM ACQUISITION CORP·Filed 2002·Granted Aug 22, 2006·7 cites·35 claims
- 1357US5363485ABus interface having single and multiple channel FIFO devices using pending channel information stored in a circular queue for transfer of information thereinXEROX CORP·Filed 1992·Granted Nov 8, 1994·35 cites·1 claims
- 1455US5335326AMultichannel FIFO device channel sequencerXEROX CORP·Filed 1992·Granted Aug 2, 1994·32 cites·1 claims
- 1552US7107381B2Flexible data transfer to and from external device of system-on-chipPMC SIERRA INC·Filed 2002·Granted Sep 12, 2006·4 cites·21 claims
- 1650US7436954B2Security system with an intelligent DMA controllerCAVIUM NETWORKS INC·Filed 2002·Granted Oct 14, 2008·2 cites·72 claims
- 1747US5541932ACircuit for freezing the data in an interface bufferXEROX CORP·Filed 1995·Granted Jul 30, 1996·21 cites·1 claims
- 1839US7653763B2Subsystem boot and peripheral data transfer architecture for a subsystem of a system-on- chipCAVIUM NETWORKS INC·Filed 2002·Granted Jan 26, 2010·0 cites·20 claims
- 1934US5555433ACircuit for interfacing data bussesXEROX CORP·Filed 1994·Granted Sep 10, 1996·6 cites·1 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →