Inventor · disambiguated record
Antonio Luis Pacheco Rotondaro
Also filed as: PACHECO ROTONDARO ANTONIO L · PACHECO ROTONDARO ANTONIO LUIS
7 granted patents·4 pending applications·107 citations·filing 2002–2024
84Inventor score
Top patents by PatentIndex Score
11 records- 0192US12444606B2Methods for forming vertically layered ionic liquid crystal (ILC) structures on a semiconductor substrateTOKYO ELECTRON LTD·Filed 2023·Granted Oct 14, 2025·2 cites·20 claims
- 0291US7026232B1Systems and methods for low leakage strained-channel transistorTEXAS INSTRUMENTS INC·Filed 2004·Granted Apr 11, 2006·83 cites·22 claims
- 0384US8049254B2Semiconductor device with gate-undercutting recessed regionTEXAS INSTRUMENTS INC·Filed 2009·Granted Nov 1, 2011·7 cites·8 claims
- 0481US7291527B2Work function control of metalsTEXAS INSTRUMENTS INC·Filed 2005·Granted Nov 6, 2007·8 cites·7 claims
- 0569US8329589B2Semiconductor device with gate-undercutting recessed regionPACHECO ROTONDARO ANTONIO LUIS·Filed 2011·Granted Dec 11, 2012·3 cites·14 claims
- 0654US2025224282A1Integrated optical nanothermometry for real-time wafer temperature monitoring during processingTOKYO ELECTRON LTD·Filed 2024·Application pending·0 cites
- 0749US7015088B2High-K gate dielectric defect gettering using dopantsTEXAS INSTRUMENTS INC·Filed 2002·Granted Mar 21, 2006·4 cites·15 claims
- 0849US2007166906A1Method to Reduce Transistor Gate to Source/Drain Overlap Capacitance by Incorporation of CarbonTEXAS INSTRUMENTS INC·Filed 2007·Application pending·0 cites
- 0943US8288805B2Semiconductor device with gate-undercutting recessed regionPACHECO ROTONDARO ANTONIO LUIS·Filed 2011·Granted Oct 16, 2012·0 cites·7 claims
- 1038US2006113604A1Methods for reduced circuit area and improved gate length controlTEXAS INSTRUMENTS INC·Filed 2004·Application pending·0 cites
- 1133US2004126944A1Methods for forming interfacial layer for deposition of high-k dielectricsFiled 2002·Application pending·0 cites
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