Inventor · disambiguated record
Robert Alan Philhower
Also filed as: PHILHOWER ROBERT · PHILHOWER ROBERT A · PHILHOWER ROBERT ALAN
22 granted patents·5 pending applications·240 citations·filing 1997–2019
95Inventor score
Top patents by PatentIndex Score
27 records- 0193US7512772B2Soft error handling in microprocessorsIBM·Filed 2007·Granted Mar 31, 2009·35 cites·2 claims
- 0290US7627742B2Method and apparatus for conserving power by throttling instruction fetching when a processor encounters low confidence branches in an information handling systemIBM·Filed 2007·Granted Dec 1, 2009·27 cites·17 claims
- 0390US7401242B2Dynamic power management in a processor designIBM·Filed 2005·Granted Jul 15, 2008·22 cites·7 claims
- 0485US11157280B2Dynamic fusion based on operand sizeIBM·Filed 2017·Granted Oct 26, 2021·4 cites·20 claims
- 0585US7490224B2Time-of-life counter design for handling instruction flushes from a queueIBM·Filed 2005·Granted Feb 10, 2009·13 cites·3 claims
- 0682US7681056B2Dynamic power management in a processor designIBM·Filed 2008·Granted Mar 16, 2010·10 cites·7 claims
- 0779US10037207B2Power management of branch predictors in a computer processorIBM·Filed 2016·Granted Jul 31, 2018·2 cites·7 claims
- 0879US8006070B2Method and apparatus for inhibiting fetch throttling when a processor encounters a low confidence branch instruction in an information handling systemIBM·Filed 2007·Granted Aug 23, 2011·9 cites·20 claims
- 0978US9996351B2Power management of branch predictors in a computer processorIBM·Filed 2016·Granted Jun 12, 2018·2 cites·10 claims
- 1077US8255669B2Method and apparatus for thread priority control in a multi-threaded processor based upon branch issue information including branch confidence informationGSCHWIND MICHAEL KARL·Filed 2008·Granted Aug 28, 2012·8 cites·9 claims
- 1177US7925853B2Method and apparatus for controlling memory array gating when a processor executes a low confidence branch instruction in an information handling systemIBM·Filed 2008·Granted Apr 12, 2011·8 cites·20 claims
- 1272US6131182AMethod and apparatus for synthesizing and optimizing control logic based on SRCMOS logic array macrosIBM·Filed 1997·Granted Oct 10, 2000·72 cites·31 claims
- 1371US10740104B2Tagging target branch predictors with context with index modification and late stop fetch on tag mismatchIBM·Filed 2018·Granted Aug 11, 2020·1 cites·17 claims
- 1471US7797521B2Method, system, and computer program product for path-correlated indirect address predictionsIBM·Filed 2007·Granted Sep 14, 2010·5 cites·19 claims
- 1570US10579384B2Effective address based instruction fetch unit for out of order processorsIBM·Filed 2017·Granted Mar 3, 2020·1 cites·20 claims
- 1670US7913070B2Time-of-life counter for handling instruction flushes from a queueIBM·Filed 2008·Granted Mar 22, 2011·4 cites·2 claims
- 1766US7725659B2Alignment of cache fetch return data relative to a threadIBM·Filed 2007·Granted May 25, 2010·3 cites·21 claims
- 1863US7370176B2System and method for high frequency stall designIBM·Filed 2005·Granted May 6, 2008·2 cites·6 claims
- 1959US10552159B2Power management of branch predictors in a computer processorIBM·Filed 2018·Granted Feb 4, 2020·0 cites·17 claims
- 2059US6785703B2Simultaneous dual rail static carry-save-adder circuit using silicon on insulator technologyIBM·Filed 2001·Granted Aug 31, 2004·7 cites·14 claims
- 2154US6711633B24:2 compressor circuit for use in an arithmetic unitIBM·Filed 2002·Granted Mar 23, 2004·5 cites·24 claims
- 2252US2008148021A1High Frequency Stall DesignDEMENT JONATHAN JAMES·Filed 2008·Application pending·0 cites
- 2348US2010031011A1Method and apparatus for optimized method of bht banking and multiple updatesIBM·Filed 2008·Application pending·0 cites
- 2447US11074379B2Multi-cycle latch tree synthesisIBM·Filed 2019·Granted Jul 27, 2021·0 cites·20 claims
- 2547US2009193240A1Method and apparatus for increasing thread priority in response to flush information in a multi-threaded processor of an information handling systemIBM·Filed 2008·Application pending·0 cites
- 2640US2008127019A1Method and system for designing a memory registerIBM·Filed 2006·Application pending·0 cites
- 2735US2008164933A1Method and apparatus for multiple array low-power operation modesIBM·Filed 2007·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →