Inventor · disambiguated record
Yves Chabal
Also filed as: CHABAL YVES · CHABAL YVES J · CHABAL YVES JEAN
6 granted patents·1 pending application·104 citations·filing 1998–2017
81Inventor score
Files withAGERE SYSTEMS INC4AGERE SYST GUARDIAN CORP1BOARD OF REGENTS THE UNIV OF TEXAS SYTEM1VERSUM MAT US LLC1
Top patents by PatentIndex Score
7 records- 0189US6723581B1Semiconductor device having a high-K gate dielectric and method of manufacture thereofAGERE SYSTEMS INC·Filed 2002·Granted Apr 20, 2004·48 cites·20 claims
- 0273US6825538B2Semiconductor device using an insulating layer having a seed layerAGERE SYSTEMS INC·Filed 2002·Granted Nov 30, 2004·15 cites·5 claims
- 0370US6388290B1Single crystal silicon on polycrystalline silicon integrated circuitsAGERE SYST GUARDIAN CORP·Filed 1998·Granted May 14, 2002·40 cites·7 claims
- 0447US7223677B2Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrateAGERE SYSTEMS INC·Filed 2004·Granted May 29, 2007·1 cites·17 claims
- 0546US12163224B2Methods for depositing a conformal metal or metalloid silicon nitride filmVERSUM MAT US LLC·Filed 2016·Granted Dec 10, 2024·0 cites·5 claims
- 0643US11173470B2Storing molecule within porous materials with a surface molecular barrier layerBOARD OF REGENTS THE UNIV OF TEXAS SYTEM·Filed 2017·Granted Nov 16, 2021·0 cites·13 claims
- 0741US2004099889A1Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrateAGERE SYSTEMS INC·Filed 2002·Application pending·0 cites
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