Inventor · disambiguated record
Tapan Jyoti Chakraborty
Also filed as: CHAKRABORTY TAPAN · CHAKRABORTY TAPAN J · CHAKRABORTY TAPAN JYOTI
20 granted patents·381 citations·filing 1992–2019
95Inventor score
Top patents by PatentIndex Score
20 records- 0193US7482831B2Soft error tolerant flip flopsALCATEL LUCENT USA INC·Filed 2006·Granted Jan 27, 2009·46 cites·14 claims
- 0291US6148425ABist architecture for detecting path-delay faults in a sequential circuitLUCENT TECHNOLOGIES INC·Filed 1998·Granted Nov 14, 2000·95 cites·8 claims
- 0386US7594150B2Fault-tolerant architecture of flip-flops for transient pulses and signal delaysALCATEL LUCENT USA INC·Filed 2006·Granted Sep 22, 2009·20 cites·17 claims
- 0486US5606567ADelay testing of high-performance digital components by a slow-speed testerLUCENT TECHNOLOGIES INC·Filed 1994·Granted Feb 25, 1997·61 cites·23 claims
- 0583US7962885B2Method and apparatus for describing components adapted for dynamically modifying a scan path for system-on-chip testingALCATEL LUCENT USA INC·Filed 2007·Granted Jun 14, 2011·12 cites·19 claims
- 0681US7284159B2Fault injection method and systemLUCENT TECHNOLOGIES INC·Filed 2003·Granted Oct 16, 2007·27 cites·11 claims
- 0780US7949915B2Method and apparatus for describing parallel access to a system-on-chipALCATEL LUCENT USA INC·Filed 2007·Granted May 24, 2011·11 cites·21 claims
- 0873US5499249AMethod and apparatus for test generation and fault simulation for sequential circuits with embedded random access memories (RAMs)AT & T CORP·Filed 1994·Granted Mar 12, 1996·34 cites·6 claims
- 0971US10249380B2Embedded memory testing with storage borrowingQUALCOMM INC·Filed 2017·Granted Apr 2, 2019·3 cites·24 claims
- 1071US7958417B2Apparatus and method for isolating portions of a scan path of a system-on-chipALCATEL LUCENT USA INC·Filed 2008·Granted Jun 7, 2011·6 cites·21 claims
- 1171US7689866B2Method and apparatus for injecting transient hardware faults for software testingALCATEL LUCENT USA INC·Filed 2006·Granted Mar 30, 2010·6 cites·25 claims
- 1270US10429441B2Efficient test architecture for multi-die chipsQUALCOMM INC·Filed 2017·Granted Oct 1, 2019·1 cites·11 claims
- 1364US7958479B2Method and apparatus for describing and testing a system-on-chipALCATEL LUCENT USA INC·Filed 2007·Granted Jun 7, 2011·4 cites·24 claims
- 1461US7954022B2Apparatus and method for controlling dynamic modification of a scan pathALCATEL LUCENT USA INC·Filed 2008·Granted May 31, 2011·3 cites·20 claims
- 1555US6378094B1Method and system for testing cluster circuits in a boundary scan environmentLUCENT TECHNOLOGIES INC·Filed 1999·Granted Apr 23, 2002·18 cites·12 claims
- 1651US5365528AMethod for testing delay faults in non-scan sequential circuitsAT & T BELL LAB·Filed 1992·Granted Nov 15, 1994·15 cites·8 claims
- 1750US11041904B2Zero-pin test solution for integrated circuitsQUALCOMM INC·Filed 2019·Granted Jun 22, 2021·0 cites·20 claims
- 1847US9285418B2Method and apparatus for characterizing thermal marginality in an integrated circuitQUALCOMM INC·Filed 2013·Granted Mar 15, 2016·0 cites·47 claims
- 1943US6124715ATesting of live circuit boardsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Sep 26, 2000·10 cites·13 claims
- 2035US6167542AArrangement for fault detection in circuit interconnectionsLUCENT TECHNOLOGIES INC·Filed 1998·Granted Dec 26, 2000·9 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →