Inventor · disambiguated record
Chandra Thimmannagari
Also filed as: THIMMANNAGARI CHANDRA M R · THIMMANNAGARI CHANDRA MOHAN RE
9 granted patents·12 pending applications·83 citations·filing 2002–2003
86Inventor score
Technology areasG06F
Top patents by PatentIndex Score
21 records- 0181US7340590B1Handling register dependencies between instructions specifying different width registersSUN MICROSYSTEMS INC·Filed 2003·Granted Mar 4, 2008·33 cites·30 claims
- 0269US7191316B2Method and a system for using same set of registers to handle both single and double precision floating point instructions in an instruction streamSUN MICROSYSTEMS INC·Filed 2003·Granted Mar 13, 2007·16 cites·22 claims
- 0363US7203821B2Method and apparatus to handle window management instructions without post serialization in an out of order multi-issue processor supporting multiple strandsSUN MICROSYSTEMS INC·Filed 2003·Granted Apr 10, 2007·11 cites·20 claims
- 0463US7065635B1Method for handling condition code modifiers in an out-of-order multi-issue multi-stranded processorSUN MICROSYSTEMS INC·Filed 2003·Granted Jun 20, 2006·10 cites·15 claims
- 0557US7380110B1Branch prediction structure with branch direction entries that share branch prediction qualifier entriesSUN MICROSYSTEMS INC·Filed 2003·Granted May 27, 2008·6 cites·29 claims
- 0654US7124284B2Method and apparatus for processing a complex instruction for execution and retirementSUN MICROSYSTEMS INC·Filed 2003·Granted Oct 17, 2006·4 cites·19 claims
- 0753US7080237B2Register window flattening logic for dependency checking among instructionsSUN MICROSYSTEMS INC·Filed 2002·Granted Jul 18, 2006·3 cites·5 claims
- 0843US7219218B2Vector technique for addressing helper instruction groups associated with complex instructionsSUN MICROSYSTEMS INC·Filed 2003·Granted May 15, 2007·0 cites·53 claims
- 0943US2004193844A1Load and/or store queue emptying technique to facilitate atomicity in processor execution of helper setSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 1043US2004193845A1Stall technique to facilitate atomicity in processor execution of helper setSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 1142US6810473B2Replacement algorithm for a replicated fully associative translation look-aside bufferSUN MICROSYSTEMS INC·Filed 2003·Granted Oct 26, 2004·0 cites·13 claims
- 1242US2004153631A1Method to handle instructions that use non-windowed registers in a windowed microprocessor capable of out-of-order executionFiled 2003·Application pending·0 cites
- 1342US2004215941A1Method and system to handle register window fill and spillSUN MICROSYSTEMS INC·Filed 2003·Application pending·0 cites
- 1442US2004162972A1Method for handling control transfer instruction couples in out-of-order, multi-issue, multi-stranded processorFiled 2003·Application pending·0 cites
- 1542US2004199749A1Method and apparatus to limit register file read ports in an out-of-order, multi-stranded processorFiled 2003·Application pending·0 cites
- 1642US2004128488A1Strand switching algorithm to avoid strand starvationFiled 2002·Application pending·0 cites
- 1742US2004128476A1Scheme to simplify instruction buffer logic supporting multiple strandsFiled 2002·Application pending·0 cites
- 1841US2004148497A1Method and apparatus for determining an early reifetch address of a mispredicted conditional branch instruction in an out of order multi-issue processorVAHIDSAFA ALI·Filed 2003·Application pending·0 cites
- 1941US2004044881A1Method and system for early speculative store-load bypassSUN MICROSYSTEMS INC·Filed 2002·Application pending·0 cites
- 2038US2004181651A1Issue bandwidth in a multi-issue out-of-order processorFiled 2003·Application pending·0 cites
- 2138US2004148496A1Method for handling a conditional move instruction in an out of order multi-issue processorFiled 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →