Inventor · disambiguated record
Ting Chieh Su
Also filed as: SU TING CHIEH
4 granted patents·1 pending application·10 citations·filing 2006–2023
65Inventor score
Top patents by PatentIndex Score
5 records- 0171US7642602B2System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistorsSEMICONDUCTOR MFG INT SHANGHAI·Filed 2006·Granted Jan 5, 2010·5 cites·8 claims
- 0266US8686507B2System and method for I/O ESD protection with floating and/or biased polysilicon regionsSU TING CHIEH·Filed 2006·Granted Apr 1, 2014·5 cites·12 claims
- 0360US2024241517A1Path planning method and autonomous traveling robotWISTRON CORP·Filed 2023·Application pending·0 cites
- 0446US8283726B2System and method for I/O ESD protection with polysilicon regions fabricated by processes for making core transistorsSU TING CHIEH·Filed 2009·Granted Oct 9, 2012·0 cites·10 claims
- 0533US8319286B2System and method for input pin ESD protection with floating and/or biased polysilicon regionsSU TING CHIEH·Filed 2010·Granted Nov 27, 2012·0 cites·10 claims
Join the waitlist — get patent alerts
Get an alert when Ting Chieh Su files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →