Inventor · disambiguated record
Jeffrey S. Salowe
Also filed as: SALOWE JEFFREY · SALOWE JEFFREY S · SALOWE JEFFREY SCOTT
27 granted patents·445 citations·filing 1999–2016
97Inventor score
Top patents by PatentIndex Score
27 records- 0196US8375348B1Method, system, and program product to implement colored tiles for detail routing for double pattern lithographyCADENCE DESIGN SYSTEMS INC·Filed 2010·Granted Feb 12, 2013·41 cites·24 claims
- 0295US8560998B1Method, system, and program product to implement C-routing for double pattern lithographySALOWE JEFFREY SCOTT·Filed 2010·Granted Oct 15, 2013·43 cites·21 claims
- 0393US8671368B1Method, system, and program product to implement detail routing for double pattern lithographySALOWE JEFFREY SCOTT·Filed 2010·Granted Mar 11, 2014·29 cites·30 claims
- 0492US9251299B1Methods, systems, and articles of manufacture for associating track patterns with rules for electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Feb 2, 2016·17 cites·20 claims
- 0591US9117052B1Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patternsCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 25, 2015·15 cites·22 claims
- 0691US8984465B1Methods, systems, and articles of manufacture for automatically assigning track patterns to regions for physical implementation of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Mar 17, 2015·16 cites·27 claims
- 0790US9165103B1Methods, systems, and articles of manufacture for tessellating and labeling routing space for routing electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Oct 20, 2015·14 cites·20 claims
- 0890US9003349B1Methods, systems, and articles of manufacture for implementing a physical electronic design with area-bounded tracksCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Apr 7, 2015·14 cites·25 claims
- 0990US7594214B1Maximum flow analysis for electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2006·Granted Sep 22, 2009·23 cites·32 claims
- 1089US10049175B1Methods, systems, and articles of manufacture for interactively implementing physical electronic designs with track patternsCADENCE DESIGN SYSTEMS INC·Filed 2015·Granted Aug 14, 2018·6 cites·20 claims
- 1188US9384317B1Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniquesCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Jul 5, 2016·12 cites·32 claims
- 1288US9213793B1Methods, systems, and articles of manufacture for implementing electronic designs using flexible routing tracksCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Dec 15, 2015·11 cites·30 claims
- 1387US8640080B1Method and system for visualizing pin access locationsSALOWE JEFFREY S·Filed 2012·Granted Jan 28, 2014·13 cites·27 claims
- 1484US9754072B1Methods, systems, and articles of manufacture for implementing electronic designs using constraint driven techniquesCADENCE DESIGN SYSTEMS INC·Filed 2016·Granted Sep 5, 2017·4 cites·20 claims
- 1582US7089526B1Maximum flow analysis for electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 8, 2006·29 cites·24 claims
- 1681US9104830B1Methods, systems, and articles of manufacture for assigning track patterns to regions of an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2013·Granted Aug 11, 2015·6 cites·20 claims
- 1780US8065652B1Method and system for determining hard and preferred rules in global routing of electronic designsSALOWE JEFFREY SCOTT·Filed 2007·Granted Nov 22, 2011·15 cites·53 claims
- 1878US8935649B1Methods, systems, and articles of manufacture for routing an electronic design using spacetilesSALOWE JEFFREY S·Filed 2012·Granted Jan 13, 2015·5 cites·27 claims
- 1976US9817941B2Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2014·Granted Nov 14, 2017·4 cites·20 claims
- 2076US9183343B1Methods, systems, and articles of manufacture for implementing high current carrying interconnects in electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2012·Granted Nov 10, 2015·7 cites·29 claims
- 2176US7100128B1Zone tree method and mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 29, 2006·23 cites·36 claims
- 2276US6981235B1Nearest neighbor mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Dec 27, 2005·23 cites·27 claims
- 2372US8117569B1Method and mechanism for implementing a minimum spanning treeSALOWE JEFFREY SCOTT·Filed 2009·Granted Feb 14, 2012·4 cites·20 claims
- 2470US7100129B1Hierarchical gcell method and mechanismCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 29, 2006·14 cites·42 claims
- 2568US9075932B1Methods and systems for routing an electronic design using spacetilesSALOWE JEFFREY S·Filed 2012·Granted Jul 7, 2015·2 cites·21 claims
- 2666US7676781B1Method and mechanism for implementing a minimum spanning treeCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Mar 9, 2010·9 cites·19 claims
- 2766US6543041B1Method and apparatus for reducing signal integrity and reliability problems in ICS through netlist changes during placementCADENCE DESIGN SYSTEMS INC·Filed 1999·Granted Apr 1, 2003·46 cites·30 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →