Inventor · disambiguated record
Jiasheng Chen
Also filed as: CHEN JIASHENG
30 granted patents·28 pending applications·17 citations·filing 2016–2025
93Inventor score
Files withINTEL CORP31ADVANCED MICRO DEVICES INC21WISTRON CORP3NR ELECTRIC CO LTD2HUAWEI TECH CO LTD1
Top patents by PatentIndex Score
58 records- 0196US11842423B2Dot product operations on sparse matrix elementsINTEL CORP·Filed 2020·Granted Dec 12, 2023·4 cites·22 claims
- 0287US2025104180A1Architecture for block sparse operations on a systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 0387US2025166114A1Architecture for block sparse operations on a systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 0485US12198222B2Architecture for block sparse operations on a systolic arrayINTEL CORP·Filed 2023·Granted Jan 14, 2025·0 cites·20 claims
- 0585US10509596B2Extreme-bandwidth scalable performance-per-watt GPU architectureADVANCED MICRO DEVICES INC·Filed 2017·Granted Dec 17, 2019·4 cites·17 claims
- 0682US12189571B2Dual pipeline parallel systolic arrayINTEL CORP·Filed 2021·Granted Jan 7, 2025·1 cites·20 claims
- 0780US2025199863A1Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2024·Application pending·0 cites
- 0877US10817302B2Processor support for bypassing vector source operandsADVANCED MICRO DEVICES INC·Filed 2017·Granted Oct 27, 2020·2 cites·20 claims
- 0974US2025053613A1Random sparsity handling in a systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 1073US11768664B2Processing unit with mixed precision operationsADVANCED MICRO DEVICES INC·Filed 2019·Granted Sep 26, 2023·1 cites·20 claims
- 1173US10701545B2File sending method and terminal, and file receiving method and terminalHUAWEI TECH CO LTD·Filed 2016·Granted Jun 30, 2020·3 cites·20 claims
- 1273US2025117359A1Dual pipeline parallel systolic arrayINTEL CORP·Filed 2024·Application pending·0 cites
- 1371US10656951B2Pipeline including separate hardware data paths for different instruction typesADVANCED MICRO DEVICES INC·Filed 2017·Granted May 19, 2020·1 cites·20 claims
- 1470US2024111530A1Matrix multiplication unit with flexible precision operationsADVANCED MICRO DEVICES INC·Filed 2023·Application pending·0 cites
- 1569US11789732B2Arithmetic logic unit register sequencingADVANCED MICRO DEVICES INC·Filed 2022·Granted Oct 17, 2023·0 cites·20 claims
- 1668US10929944B2Low power and low latency GPU coprocessor for persistent computingADVANCED MICRO DEVICES INC·Filed 2016·Granted Feb 23, 2021·1 cites·20 claims
- 1767US12190158B2Using sparsity metadata to reduce systolic array power consumptionINTEL CORP·Filed 2021·Granted Jan 7, 2025·0 cites·20 claims
- 1866US11625807B2Low power and low latency GPU coprocessor for persistent computingADVANCED MICRO DEVICES INC·Filed 2021·Granted Apr 11, 2023·0 cites·20 claims
- 1966US2025231764A1Large integer multiplication enhancements for graphics environmentINTEL CORP·Filed 2025·Application pending·0 cites
- 2064US12236238B2Large integer multiplication enhancements for graphics environmentINTEL CORP·Filed 2021·Granted Feb 25, 2025·0 cites·22 claims
- 2164US12086205B2Random sparsity handling in a systolic arrayINTEL CORP·Filed 2021·Granted Sep 10, 2024·0 cites·20 claims
- 2263US11237827B2Arithemetic logic unit register sequencingADVANCED MICRO DEVICES INC·Filed 2019·Granted Feb 1, 2022·0 cites·20 claims
- 2362US11762658B2Matrix multiplication unit with flexible precision operationsADVANCED MICRO DEVICES INC·Filed 2019·Granted Sep 19, 2023·0 cites·20 claims
- 2461US11494192B2Pipeline including separate hardware data paths for different instruction typesADVANCED MICRO DEVICES INC·Filed 2020·Granted Nov 8, 2022·0 cites·29 claims
- 2560US12254236B2Video transmission method and displayWISTRON CORP·Filed 2023·Granted Mar 18, 2025·0 cites·20 claims
- 2658US2025036361A1Floating-point conversion via an integer unitINTEL CORP·Filed 2023·Application pending·0 cites
- 2757US12394393B2Display system and operation method for display systemWISTRON CORP·Filed 2023·Granted Aug 19, 2025·0 cites·19 claims
- 2857US12340730B2Display device and operation method for display deviceWISTRON CORP·Filed 2023·Granted Jun 24, 2025·0 cites·19 claims
- 2957US2025068473A1Distributed register file cache to reduce l1 bandwidth requirementsINTEL CORP·Filed 2023·Application pending·0 cites
- 3057US2025291550A1Hardware accelerated random number generationINTEL CORP·Filed 2024·Application pending·0 cites
- 3156US12487824B2Immediate offset of load store and atomic instructionsINTEL CORP·Filed 2021·Granted Dec 2, 2025·0 cites·20 claims
- 3255US11630667B2Dedicated vector sub-processor systemADVANCED MICRO DEVICES INC·Filed 2019·Granted Apr 18, 2023·0 cites·18 claims
- 3354US2025110733A1Conversion operations and special value use cases supporting 8-bit floating point format in a graphics architectureINTEL CORP·Filed 2023·Application pending·0 cites
- 3453US2025085969A1Unblocking the integer pipeline during math pipeline phases in a graphics environmentINTEL CORP·Filed 2023·Application pending·0 cites
- 3552US2024168764A1Supporting and load balancing multiple double precision pipelines in a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 3651US2025036412A1Avoiding the use of a result crossbar when down converting to packed register formatsINTEL CORP·Filed 2023·Application pending·0 cites
- 3751US2025110741A1Supporting 8-bit floating point format for parallel computing and stochastic rounding operations in a graphics architectureINTEL CORP·Filed 2023·Application pending·0 cites
- 3851US2024220448A1Scalable and configurable clustered systolic arrayINTEL CORP·Filed 2022·Application pending·0 cites
- 3951US2025068423A1Instruction encoding to implement increased register capacity per threadINTEL CORP·Filed 2023·Application pending·0 cites
- 4051US2025037347A132-bit channel-aligned integer multiplication via multiple multipliers per-channelINTEL CORP·Filed 2023·Application pending·0 cites
- 4149US2024111826A1Hardware enhancements for double precision systolic supportINTEL CORP·Filed 2022·Application pending·0 cites
- 4249US2024103810A1Supporting vector multiply add with double accumulator access in a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 4348US11347827B2Hybrid matrix multiplication pipelineADVANCED MICRO DEVICES INC·Filed 2019·Granted May 31, 2022·0 cites·20 claims
- 4448US2024169021A1Enhancements for accumulator usage and instruction forwarding in matrix multiply pipeline in graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 4548US2024160478A1Increasing processing resources in processing cores of a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
- 4647US2021096877A1Collapsing bubbles in a processing unit pipelineADVANCED MICRO DEVICES INC·Filed 2019·Application pending·0 cites
- 4746US12067401B2Stream processor with low power parallel matrix multiply pipelineADVANCED MICRO DEVICES INC·Filed 2017·Granted Aug 20, 2024·0 cites·20 claims
- 4846US11880683B2Packed 16 bits instruction pipelineADVANCED MICRO DEVICES INC·Filed 2017·Granted Jan 23, 2024·0 cites·20 claims
- 4946US11409536B2Pairing SIMD lanes to perform double precision operationsADVANCED MICRO DEVICES INC·Filed 2016·Granted Aug 9, 2022·0 cites·20 claims
- 5046US2024111825A1Single precision support for systolic pipeline in a graphics environmentINTEL CORP·Filed 2022·Application pending·0 cites
Showing the top 50 of 58 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →