Inventor · disambiguated record
Somasunder Kattepura Sreenath
Also filed as: SREENATH SOMASUNDER KATTEPURA
6 granted patents·1 pending application·35 citations·filing 2006–2023
80Inventor score
Top patents by PatentIndex Score
7 records- 0180US9065430B2Architecture for VBUS pulsing in UDSM processesTEXAS INSTRUMENTS INC·Filed 2014·Granted Jun 23, 2015·5 cites·18 claims
- 0279US8054103B1Synchronous clock multiplexing and output-enableTEXAS INSTRUMENTS INC·Filed 2010·Granted Nov 8, 2011·7 cites·16 claims
- 0378US7522003B2Constant margin CMOS biasing circuitTEXAS INSTRUMENTS INC·Filed 2006·Granted Apr 21, 2009·11 cites·12 claims
- 0471US8704550B2Architecture for VBUS pulsing in UDSM processesSETH SUMANTRA·Filed 2007·Granted Apr 22, 2014·6 cites·14 claims
- 0566US7332965B2Gate leakage insensitive current mirror circuitTEXAS INSTRUMENTS INC·Filed 2006·Granted Feb 19, 2008·6 cites·27 claims
- 0643US2024338287A1Ser-des test chip and method for managing inter-operability data rate rangeSAMSUNG ELECTRONICS CO LTD·Filed 2023·Application pending·0 cites
- 0741US9465759B2Universal serializer architectureTEXAS INSTRUMENTS INC·Filed 2014·Granted Oct 11, 2016·0 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →