Inventor · disambiguated record
Chong Wee Lim
Also filed as: LIM CHONG W · LIM CHONG WEE
11 granted patents·1 pending application·493 citations·filing 1998–2007
93Inventor score
Top patents by PatentIndex Score
12 records- 0196US7888240B2Method of forming phase change memory devices in a pulsed DC deposition chamberST MICROELECTRONICS SRL·Filed 2007·Granted Feb 15, 2011·57 cites·19 claims
- 0292US6228727B1Method to form shallow trench isolations with rounded corners and reduced trench oxide recessCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted May 8, 2001·142 cites·18 claims
- 0388US6350661B2Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Feb 26, 2002·49 cites·5 claims
- 0484US6265302B1Partially recessed shallow trench isolation method for fabricating borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Jul 24, 2001·77 cites·17 claims
- 0582US6165871AMethod of making low-leakage architecture for sub-0.18 μm salicided CMOS deviceCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Dec 26, 2000·55 cites·26 claims
- 0675US6093628AUltra-low sheet resistance metal/poly-si gate for deep sub-micron CMOS applicationCHARTERED SEMICONDUCTOR MFG·Filed 1998·Granted Jul 25, 2000·41 cites·19 claims
- 0774US6271133B1Optimized Co/Ti-salicide scheme for shallow junction deep sub-micron device fabricationCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Aug 7, 2001·36 cites·6 claims
- 0863US6846359B2Epitaxial CoSi2 on MOS devicesUNIV ILLINOIS·Filed 2002·Granted Jan 25, 2005·5 cites·18 claims
- 0958US6297126B1Silicon nitride capped shallow trench isolation method for fabricating sub-micron devices with borderless contactsCHARTERED SEMICONDUCTOR MFG·Filed 1999·Granted Oct 2, 2001·20 cites·11 claims
- 1055US6797598B2Method for forming an epitaxial cobalt silicide layer on MOS devicesUNIV ILLINOIS·Filed 2002·Granted Sep 28, 2004·8 cites·16 claims
- 1149US6762131B2Method for large-scale fabrication of atomic-scale structures on material surfaces using surface vacanciesUNIV ILLINOIS·Filed 2002·Granted Jul 13, 2004·3 cites·22 claims
- 1236US2004224469A1Method for forming a strained semiconductor substrateUNIV ILLINOIS·Filed 2003·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →