Inventor · disambiguated record
Elias Lee Fallon
Also filed as: FALLON ELIAS · FALLON ELIAS L · FALLON ELIAS LEE
20 granted patents·1 pending application·340 citations·filing 2002–2023
95Inventor score
Top patents by PatentIndex Score
21 records- 0197US7543262B2Analog layout module generator and methodCADENCE DESIGN SYSTEMS INC·Filed 2005·Granted Jun 2, 2009·138 cites·24 claims
- 0295US10699051B1Method and system for performing cross-validation for model-based layout recommendationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Jun 30, 2020·32 cites·20 claims
- 0395US10628546B1Method and system for automatically extracting layout design patterns for custom layout design reuse through interactive recommendationsCADENCE DESIGN SYSTEMS INC·Filed 2018·Granted Apr 21, 2020·28 cites·20 claims
- 0494US8732640B1Methods, systems, and articles for multi-scenario physically-aware design methodology for layout-dependent effectsKRISHNAN PRAKASH·Filed 2011·Granted May 20, 2014·39 cites·44 claims
- 0589US11620548B1System, method, and computer program product for predicting parasitics in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2020·Granted Apr 4, 2023·4 cites·20 claims
- 0687US11003825B1System, method, and computer program product for optimization in an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted May 11, 2021·6 cites·15 claims
- 0786US9064063B1Methods, systems, and articles of manufacture for implementing interactive, real-time checking or verification of complex constraintsYU HENRY·Filed 2012·Granted Jun 23, 2015·13 cites·31 claims
- 0885US11087060B1System, method, and computer program product for the integration of machine learning predictors in an automatic placement associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Aug 10, 2021·6 cites·17 claims
- 0982US11048852B1System, method and computer program product for automatic generation of sizing constraints by reusing existing electronic designsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jun 29, 2021·4 cites·13 claims
- 1081US9298871B1Method and system for implementing translations of parameterized cellsFALLON ELIAS L·Filed 2011·Granted Mar 29, 2016·10 cites·24 claims
- 1176US11562110B1System and method for device mismatch contribution computation for non-continuous circuit outputsCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 24, 2023·2 cites·20 claims
- 1276US11275881B1System, method, and computer program product for genetic routing in an electronic circuit designCADENCE DESIGN SYSTEMS INC·Filed 2021·Granted Mar 15, 2022·1 cites·20 claims
- 1374US11275882B1System, method, and computer program product for group and isolation prediction using machine learning and applications in analog placement and sizingCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Mar 15, 2022·2 cites·20 claims
- 1474US8694943B1Methods, systems, and computer program product for implementing electronic designs with connectivity and constraint awarenessYU HENRY·Filed 2012·Granted Apr 8, 2014·4 cites·42 claims
- 1573US7093220B2Method for generating constrained component placement for integrated circuits and packagesCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Aug 15, 2006·19 cites·38 claims
- 1670US12045730B1System, method, and computer program product for analog and mix-signal circuit placementCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jul 23, 2024·1 cites·16 claims
- 1768US6874133B2Integrated circuit design layout compaction methodCADENCE DESIGN SYSTEMS INC·Filed 2002·Granted Mar 29, 2005·14 cites·13 claims
- 1859US6918102B2Method and apparatus for exact relative positioning of devices in a semiconductor circuit layoutCADENCE DESIGN SYSTEMS INC·Filed 2003·Granted Jul 12, 2005·7 cites·22 claims
- 1958US2024202598A1Semi-automated labeling of time-series sensor dataQEEXO CO·Filed 2023·Application pending·0 cites
- 2056US11544574B1System, method, and computer program product for analog structure prediction associated with an electronic designCADENCE DESIGN SYSTEMS INC·Filed 2019·Granted Jan 3, 2023·0 cites·17 claims
- 2155US6711725B1Method of creating conformal outlines for use in transistor level semiconductor layoutsNEOLINEAR INC·Filed 2002·Granted Mar 23, 2004·10 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →