Inventor · disambiguated record
Christian Zoellin
Also filed as: ZOELLIN CHRISTIAN · ZOELLIN CHRISTIAN G · ZOELLIN CHRISTIAN GERHARD
53 granted patents·1 pending application·89 citations·filing 2012–2023
97Inventor score
Top patents by PatentIndex Score
54 records- 0198US11144319B1Redistribution of architected states for a processor register fileIBM·Filed 2020·Granted Oct 12, 2021·19 cites·20 claims
- 0297US11249757B1Handling and fusing load instructions in a processorIBM·Filed 2020·Granted Feb 15, 2022·6 cites·18 claims
- 0395US11163571B1Fusion to enhance early address generation of load instructions in a microprocessorIBM·Filed 2020·Granted Nov 2, 2021·4 cites·20 claims
- 0495US9680653B1Cipher message with authentication instructionIBM·Filed 2016·Granted Jun 13, 2017·19 cites·20 claims
- 0594US10671532B2Reducing cache transfer overhead in a systemIBM·Filed 2017·Granted Jun 2, 2020·7 cites·18 claims
- 0690US11797713B2Systems and methods for dynamic control of a secure mode of operation in a processorIBM·Filed 2020·Granted Oct 24, 2023·2 cites·24 claims
- 0788US11010298B2Reducing cache transfer overhead in a systemIBM·Filed 2020·Granted May 18, 2021·2 cites·18 claims
- 0888US10579525B2Reducing cache transfer overhead in a systemIBM·Filed 2017·Granted Mar 3, 2020·3 cites·24 claims
- 0987US11392386B2Program counter (PC)-relative load and store addressing for fused instructionsIBM·Filed 2020·Granted Jul 19, 2022·2 cites·20 claims
- 1087US10585800B2Reducing cache transfer overhead in a systemIBM·Filed 2017·Granted Mar 10, 2020·3 cites·24 claims
- 1186US11586542B2Reducing cache transfer overhead in a systemIBM·Filed 2021·Granted Feb 21, 2023·1 cites·20 claims
- 1285US10831478B2Sort and merge instruction for a general-purpose processorIBM·Filed 2018·Granted Nov 10, 2020·3 cites·20 claims
- 1383US10348506B2Determination of state of padding operationIBM·Filed 2016·Granted Jul 9, 2019·4 cites·20 claims
- 1481US9885748B2Module testing utilizing wafer probe test equipmentIBM·Filed 2015·Granted Feb 6, 2018·2 cites·18 claims
- 1580US10303759B2Memory preserving parse tree based compression with entropy codingIBM·Filed 2015·Granted May 28, 2019·2 cites·18 claims
- 1679US11892949B2Reducing cache transfer overhead in a systemIBM·Filed 2023·Granted Feb 6, 2024·0 cites·20 claims
- 1776US12223098B2Systems and methods for dynamic control of a secure mode of operation in a processorIBM·Filed 2023·Granted Feb 11, 2025·0 cites·20 claims
- 1876US10824426B2Generating and verifying hardware instruction traces including memory data contentsIBM·Filed 2019·Granted Nov 3, 2020·1 cites·20 claims
- 1974US10579332B1Hardware sort accelerator sharing first level processor cacheIBM·Filed 2018·Granted Mar 3, 2020·1 cites·20 claims
- 2072US10691412B2Parallel sort accelerator sharing first level processor cacheIBM·Filed 2018·Granted Jun 23, 2020·1 cites·17 claims
- 2171US10740104B2Tagging target branch predictors with context with index modification and late stop fetch on tag mismatchIBM·Filed 2018·Granted Aug 11, 2020·1 cites·17 claims
- 2270US9171110B2Accelerating functional verification of an integrated circuitDEINDL MICHAEL·Filed 2012·Granted Oct 27, 2015·4 cites·20 claims
- 2369US11281469B2Saving and restoring machine state between multiple executions of an instructionIBM·Filed 2020·Granted Mar 22, 2022·0 cites·20 claims
- 2469US10936318B2Tagged indirect branch predictor (TIP)IBM·Filed 2018·Granted Mar 2, 2021·1 cites·18 claims
- 2567US10949212B2Saving and restoring machine state between multiple executions of an instructionIBM·Filed 2020·Granted Mar 16, 2021·0 cites·20 claims
- 2667US9506986B2Integrated circuit chip and a method for testing the sameIBM·Filed 2014·Granted Nov 29, 2016·1 cites·16 claims
- 2764US10317465B2Integrated circuit chip and a method for testing the sameIBM·Filed 2018·Granted Jun 11, 2019·0 cites·4 claims
- 2863US10831503B2Saving and restoring machine state between multiple executions of an instructionIBM·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 2963US10719294B2Hardware sort accelerator sharing first level processor cacheIBM·Filed 2019·Granted Jul 21, 2020·0 cites·17 claims
- 3062US11221850B2Sort and merge instruction for a general-purpose processorIBM·Filed 2020·Granted Jan 11, 2022·0 cites·20 claims
- 3161US11327757B2Processor providing intelligent management of values buffered in overlaid architected and non-architected register filesIBM·Filed 2020·Granted May 10, 2022·0 cites·20 claims
- 3260US10496405B2Generating and verifying hardware instruction traces including memory data contentsIBM·Filed 2017·Granted Dec 3, 2019·0 cites·12 claims
- 3360US10360030B2Efficient pointer load and formatIBM·Filed 2017·Granted Jul 23, 2019·0 cites·5 claims
- 3460US10006965B2Integrated circuit chip and a method for testing the sameIBM·Filed 2016·Granted Jun 26, 2018·0 cites·17 claims
- 3559US10353707B2Efficient pointer load and formatIBM·Filed 2017·Granted Jul 16, 2019·0 cites·10 claims
- 3659US10331446B2Generating and verifying hardware instruction traces including memory data contentsIBM·Filed 2017·Granted Jun 25, 2019·0 cites·12 claims
- 3759US10169041B1Efficient pointer load and formatIBM·Filed 2017·Granted Jan 1, 2019·0 cites·1 claims
- 3858US10521506B2Memory preserving parse tree based compression with entropy codingIBM·Filed 2016·Granted Dec 31, 2019·0 cites·10 claims
- 3957US11308277B2Memory preserving parse tree based compression with entropy codingIBM·Filed 2019·Granted Apr 19, 2022·0 cites·20 claims
- 4056US11748104B2Microprocessor that fuses load and compare instructionsIBM·Filed 2020·Granted Sep 5, 2023·0 cites·6 claims
- 4156US11263398B2Memory preserving parse tree based compression with entropy codingIBM·Filed 2019·Granted Mar 1, 2022·0 cites·20 claims
- 4256US9891272B2Module testing utilizing wafer probe test equipmentIBM·Filed 2015·Granted Feb 13, 2018·0 cites·9 claims
- 4353US10983797B2Program instruction schedulingIBM·Filed 2019·Granted Apr 20, 2021·0 cites·17 claims
- 4452US10831502B2Migration of partially completed instructionsIBM·Filed 2018·Granted Nov 10, 2020·0 cites·20 claims
- 4551US11593108B2Sharing instruction cache footprint between multiple threadsIBM·Filed 2021·Granted Feb 28, 2023·0 cites·25 claims
- 4650US11593109B2Sharing instruction cache lines between multiple threadsIBM·Filed 2021·Granted Feb 28, 2023·0 cites·20 claims
- 4750US11416257B2Hybrid and aggregrate branch prediction system with a tagged branch orientation predictor for prediction override or pass-throughIBM·Filed 2019·Granted Aug 16, 2022·0 cites·20 claims
- 4849US10725738B2Adaptive sort accelerator sharing first level processor cacheIBM·Filed 2018·Granted Jul 28, 2020·0 cites·17 claims
- 4949US9679665B2Method for performing built-in self-testsIBM·Filed 2014·Granted Jun 13, 2017·0 cites·15 claims
- 5047US12393399B2Controlling storage accesses for merge operationsIBM·Filed 2018·Granted Aug 19, 2025·0 cites·25 claims
Showing the top 50 of 54 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →