Inventor · disambiguated record
Irving T. Ho
Also filed as: HO IRVING T · HO IRVING TZE
11 granted patents·434 citations·filing 1973–1980
93Inventor score
Files withIBM11
Top patents by PatentIndex Score
11 records- 0195US4209349AMethod for forming a narrow dimensioned mask opening on a silicon body utilizing reactive ion etchingIBM·Filed 1978·Granted Jun 24, 1980·95 cites·20 claims
- 0293US4090254ACharge injector transistor memoryIBM·Filed 1976·Granted May 16, 1978·57 cites·22 claims
- 0391US4252579AMethod for making single electrode U-MOSFET random access memory utilizing reactive ion etching and polycrystalline depositionIBM·Filed 1979·Granted Feb 24, 1981·72 cites·12 claims
- 0491US4209350AMethod for forming diffusions having narrow dimensions utilizing reactive ion etchingIBM·Filed 1978·Granted Jun 24, 1980·65 cites·18 claims
- 0585US4462040ASingle electrode U-MOSFET random access memoryIBM·Filed 1980·Granted Jul 24, 1984·60 cites·4 claims
- 0685US3943542AHigh reliability, low leakage, self-aligned silicon gate FET and method of fabricating sameIBM·Filed 1974·Granted Mar 9, 1976·30 cites·7 claims
- 0761US4014036ASingle-electrode charge-coupled random access memory cellIBM·Filed 1973·Granted Mar 22, 1977·12 cites·6 claims
- 0859US4070687AComposite channel field effect transistor and method of fabricationIBM·Filed 1977·Granted Jan 24, 1978·17 cites·4 claims
- 0958US4016431AOptimal driver for LSIIBM·Filed 1975·Granted Apr 5, 1977·8 cites·2 claims
- 1050US4017883ASingle-electrode charge-coupled random access memory cell with impurity implanted gate regionIBM·Filed 1973·Granted Apr 12, 1977·10 cites·5 claims
- 1141US4054989AHigh reliability, low leakage, self-aligned silicon gate FET and method of fabricating sameIBM·Filed 1975·Granted Oct 25, 1977·8 cites·4 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →