Inventor · disambiguated record
Atsuo Takatori
Also filed as: TAKATORI ATSUO
3 granted patents·1 pending application·20 citations·filing 2005–2011
63Inventor score
Top patents by PatentIndex Score
4 records- 0184US7952390B2Logic circuit having gated clock bufferFUJITSU SEMICONDUCTOR LTD·Filed 2009·Granted May 31, 2011·17 cites·10 claims
- 0263US8051403B2Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatusTOSHIBA KK·Filed 2007·Granted Nov 1, 2011·3 cites·11 claims
- 0344US8185863B2Delay fault test quality calculation apparatus, delay fault test quality calculation method, and delay fault test pattern generation apparatusNOZUYAMA YASUYUKI·Filed 2011·Granted May 22, 2012·0 cites·5 claims
- 0435US2005182587A1Circuit quality evaluation method and apparatus, circuit quality evaluation program, and medium having the program recorded thereonSEMICONDUCTOR TECH ACAD RES CT·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →