Inventor · disambiguated record
Jianan Yang
Also filed as: YANG JIANAN
14 granted patents·1 pending application·130 citations·filing 2008–2018
90Inventor score
Files withYANG JIANAN9FREESCALE SEMICONDUCTOR INC4RAMARAJU RAVINDRARAJ1SEMICONDUCTOR COMPONENTS IND LLC1
Top patents by PatentIndex Score
15 records- 0195US7777522B2Clocked single power supply level shifterFREESCALE SEMICONDUCTOR INC·Filed 2008·Granted Aug 17, 2010·53 cites·20 claims
- 0291US8446176B1Reconfigurable engineering change order base cellYANG JIANAN·Filed 2011·Granted May 21, 2013·35 cites·21 claims
- 0389US8766703B1Method and apparatus for sensing on-chip characteristicsYANG JIANAN·Filed 2013·Granted Jul 1, 2014·10 cites·20 claims
- 0488US8995178B1SRAM with embedded ROMYANG JIANAN·Filed 2013·Granted Mar 31, 2015·8 cites·20 claims
- 0582US8685800B2Single event latch-up prevention techniques for a semiconductor deviceYANG JIANAN·Filed 2012·Granted Apr 1, 2014·6 cites·15 claims
- 0680US8575962B2Integrated circuit having critical path voltage scaling and method thereforYANG JIANAN·Filed 2011·Granted Nov 5, 2013·7 cites·15 claims
- 0777US9026808B2Memory with word level power gatingYANG JIANAN·Filed 2012·Granted May 5, 2015·6 cites·20 claims
- 0868US9317087B2Memory column drowsy controlRAMARAJU RAVINDRARAJ·Filed 2012·Granted Apr 19, 2016·2 cites·19 claims
- 0963US10855261B2Level shifter with deterministic output during power-up sequenceSEMICONDUCTOR COMPONENTS IND LLC·Filed 2018·Granted Dec 1, 2020·2 cites·20 claims
- 1055US9899069B1Adaptable sense circuitry and method for read-only memoryFREESCALE SEMICONDUCTOR INC·Filed 2016·Granted Feb 20, 2018·1 cites·19 claims
- 1149US9123545B2Semiconductor device with single-event latch-up prevention circuitryYANG JIANAN·Filed 2014·Granted Sep 1, 2015·0 cites·18 claims
- 1245US8631292B2Multi-threading flip-flop circuitYANG JIANAN·Filed 2011·Granted Jan 14, 2014·0 cites·19 claims
- 1340US10453544B2Memory array with read only cells having multiple states and method of programming thereofFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Oct 22, 2019·0 cites·17 claims
- 1438US9691495B2Memory array with RAM and embedded ROMFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Jun 27, 2017·0 cites·20 claims
- 1536US2009302885A1Two transistor tie circuit with body biasingYANG JIANAN·Filed 2008·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →